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* Merge branch 'master' of github.com:YosysHQ/yosysEddie Hung2019-05-0121-176/+273
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| * Merge branch 'clifford/fix883'Clifford Wolf2019-05-021-0/+1
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| | * Add missing enable_undef to "sat -tempinduct-def", fixes #883Clifford Wolf2019-05-021-0/+1
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #977 from ucb-bar/fixfirrtlmemClifford Wolf2019-05-013-4/+64
| |\ | | | | | | Fix #938 - Crash occurs in case when use write_firrtl command
| | * Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-013-4/+64
| | | | | | | | | | | | | | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
| * | Fix floating point exception in qwp, fixes #923Clifford Wolf2019-05-011-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix segfault in wreduceClifford Wolf2019-04-301-0/+2
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Disabled "final loop assignment" featureClifford Wolf2019-04-301-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #972 from YosysHQ/clifford/fix968Clifford Wolf2019-04-301-0/+7
| |\ | | | | | | Add final loop variable assignment when unrolling for-loops
| | * Add final loop variable assignment when unrolling for-loops, fixes #968Clifford Wolf2019-04-301-0/+7
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #966 from YosysHQ/clifford/fix956Clifford Wolf2019-04-303-3/+55
| |\ \ | | | | | | | | Drive dangling wires with init attr with their init value
| | * | Add handling of init attributes in "opt_expr -undriven"Clifford Wolf2019-04-302-3/+42
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Drive dangling wires with init attr with their init value, fixes #956Clifford Wolf2019-04-291-0/+13
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| * | | Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinxClifford Wolf2019-04-302-156/+101
| |\ \ \ | | | | | | | | | | Refactor synth_xilinx to auto-generate doc
| | * \ \ Merge branch 'master' into eddie/refactor_synth_xilinxClifford Wolf2019-04-309-12/+40
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| * | | | Merge pull request #973 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-303-4/+4
| |\ \ \ \ | | | | | | | | | | | | Feature/python bindings cleanup
| | * \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosys into ↵Benedikt Tutzer2019-04-3088-320/+2797
| | |\ \ \ \ | | | | |_|/ | | | |/| | | | | | | | feature/python_bindings
| | * | | | Cleaned up root directoryBenedikt Tutzer2019-04-303-4/+4
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| * | | | | Include filename in "Executing Verilog-2005 frontend" message, fixes #959Clifford Wolf2019-04-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | |/ / / | |/| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | | Merge pull request #960 from YosysHQ/eddie/equiv_opt_undefClifford Wolf2019-04-291-3/+16
| |\ \ \ \ | | | | | | | | | | | | Add -undef option to equiv_opt, passed to equiv_induct
| | * | | | Add -undef option to equiv_opt, passed to equiv_inductEddie Hung2019-04-261-3/+16
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| * | | | Merge pull request #967 from olegendo/depfile_esc_spacesClifford Wolf2019-04-293-2/+17
| |\ \ \ \ | | | | | | | | | | | | escape spaces with backslash when writing dep file
| | * | | | fix codestyle formattingOleg Endo2019-04-293-14/+14
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| | * | | | escape spaces with backslash when writing dep fileOleg Endo2019-04-293-2/+17
| |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames.
| | | | * Refactor synth_xilinx to auto-generate docEddie Hung2019-04-261-153/+95
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| | | | * Cleanup ice40Eddie Hung2019-04-261-4/+6
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* | / | Copy with 1'bx padding in $shiftxEddie Hung2019-04-281-1/+11
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* / / Where did this check come from!?!Eddie Hung2019-04-261-1/+0
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* | MisspellingEddie Hung2019-04-251-1/+1
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* | Merge pull request #957 from YosysHQ/oai4fixClifford Wolf2019-04-232-2/+2
|\ \ | | | | | | Fixes for OAI4 cell implementation
| * | Fixes for OAI4 cell implementationDavid Shah2019-04-232-2/+2
| | | | | | | | | | | | | | | | | | Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah <dave@ds0.me>
* | | Format some names using inline codeEddie Hung2019-04-231-2/+2
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* | | Fix spellingEddie Hung2019-04-231-1/+1
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* | | Remove some left-over log_dump()Clifford Wolf2019-04-231-2/+0
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #914 from YosysHQ/xc7srlEddie Hung2019-04-228-41/+382
|\ \ | | | | | | synth_xilinx to now infer SRL16E/SRLC32E
| * | Update help messageEddie Hung2019-04-221-1/+1
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| * | Move 'shregmap -tech xilinx' into map_cellsEddie Hung2019-04-221-17/+20
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| * | Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-2239-71/+3146
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| * | | Tidy up, fix for -nosrlEddie Hung2019-04-212-12/+16
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| * | | Merge branch 'map_cells_before_map_luts' into xc7srlEddie Hung2019-04-211-2/+2
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| * | | | Add commentsEddie Hung2019-04-211-0/+7
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| * | | | Use new pmux2shiftx from #944, remove my old attemptEddie Hung2019-04-214-137/+8
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| * | | | Merge remote-tracking branch 'origin/clifford/pmux2shiftx' into xc7srlEddie Hung2019-04-204-0/+894
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| * \ \ \ \ Merge remote-tracking branch 'origin/master' into xc7srlEddie Hung2019-04-2027-55/+157
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| * \ \ \ \ \ Merge remote-tracking branch 'origin/pmux2shiftx' into xc7srlEddie Hung2019-04-202-0/+82
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| | * | | | | | Fix ordering of when to insert zero indexEddie Hung2019-04-111-2/+1
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| | * | | | | | More unusedEddie Hung2019-04-111-1/+0
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| | * | | | | | Remove unusedEddie Hung2019-04-111-1/+0
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| | * | | | | | FixesEddie Hung2019-04-111-20/+16
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