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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 15:35:34 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 15:35:34 -0700 |
| commit | ea0e0722bb42254ac8c63eb41664d9dfb7973aec (patch) | |
| tree | 311c8d30c696d7a39ebf380440d967f4078f52f0 | |
| parent | 408161ea3af78c747b9d45cd6482f2e4d9170085 (diff) | |
| download | yosys-ea0e0722bb42254ac8c63eb41664d9dfb7973aec.tar.gz yosys-ea0e0722bb42254ac8c63eb41664d9dfb7973aec.tar.bz2 yosys-ea0e0722bb42254ac8c63eb41664d9dfb7973aec.zip | |
Where did this check come from!?!
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 53eee7962..58dd928a0 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -275,7 +275,6 @@ struct SynthXilinxPass : public Pass Pass::call(design, "techmap -map +/xilinx/arith_map.v"); } - Pass::call(design, "hierarchy -check"); Pass::call(design, "opt -fast"); } |