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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-29 08:38:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-29 08:44:53 +0200 |
| commit | 754b1ee4b3ad8d1e1fab8eac88e0976e0355bc96 (patch) | |
| tree | 92d0c7d635c10e9bd808f39e7bfc199576f9cb45 | |
| parent | 408161ea3af78c747b9d45cd6482f2e4d9170085 (diff) | |
| download | yosys-754b1ee4b3ad8d1e1fab8eac88e0976e0355bc96.tar.gz yosys-754b1ee4b3ad8d1e1fab8eac88e0976e0355bc96.tar.bz2 yosys-754b1ee4b3ad8d1e1fab8eac88e0976e0355bc96.zip | |
Drive dangling wires with init attr with their init value, fixes #956
| -rw-r--r-- | passes/opt/opt_clean.cc | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index c38e9df5e..5d95c4f1a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -281,13 +281,26 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos maybe_del_wires.push_back(wire); } else { log_assert(GetSize(s1) == GetSize(s2)); + Const initval; + if (wire->attributes.count("\\init")) + initval = wire->attributes.at("\\init"); + if (GetSize(initval) != GetSize(wire)) + initval.bits.resize(GetSize(wire), State::Sx); RTLIL::SigSig new_conn; for (int i = 0; i < GetSize(s1); i++) if (s1[i] != s2[i]) { + if (s2[i] == State::Sx && (initval[i] == State::S0 || initval[i] == State::S1)) { + s2[i] = initval[i]; + initval[i] = State::Sx; + } new_conn.first.append_bit(s1[i]); new_conn.second.append_bit(s2[i]); } if (new_conn.first.size() > 0) { + if (initval.is_fully_undef()) + wire->attributes.erase("\\init"); + else + wire->attributes.at("\\init") = initval; used_signals.add(new_conn.first); used_signals.add(new_conn.second); module->connect(new_conn); |