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* Added log_assert() apiClifford Wolf2013-05-243-4/+6
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* Added log_abort() apiClifford Wolf2013-05-242-1/+3
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* Fixed a gcc vs. clang determinism problem in abc passClifford Wolf2013-05-231-4/+11
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* Fixed memory corruption bug in opt_rmunusedClifford Wolf2013-05-231-7/+14
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* Only initialize TCL interpreter when neededClifford Wolf2013-05-233-39/+50
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* Fixed memory leak in ilang frontendClifford Wolf2013-05-231-0/+1
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* Added missing newline to some error messagesClifford Wolf2013-05-231-2/+2
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* Added labels to "help -write-tex-command-reference-manual" outputClifford Wolf2013-05-231-0/+2
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* Added support for processes to show commandClifford Wolf2013-05-231-2/+81
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* Fixed show command for constant assignmentsClifford Wolf2013-05-231-2/+2
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* Some improvements in opt_rmdffClifford Wolf2013-05-231-2/+33
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* Merge pull request #6 from hansiglaser/masterClifford Wolf2013-05-193-4/+19
|\ | | | | added option '-Dname[=definition]' to command 'read_verilog'
| * added option '-Dname[=definition]' to command 'read_verilog'Johann Glaser2013-05-193-4/+19
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* Removed test cases that have been moved to yosys-test.Clifford Wolf2013-05-1783-18963/+0
| | | | https://github.com/cliffordwolf/yosys-tests/
* Fixed to aggressive x-folding in opt_constClifford Wolf2013-05-171-8/+21
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-05-161-8/+82
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| * Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-141-8/+82
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* | Merge branch 'bugfix'Clifford Wolf2013-05-161-2/+0
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| * Fixed synthesis of functions in latched blocksClifford Wolf2013-05-161-2/+0
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* | Some improvements in vcdcd.plClifford Wolf2013-05-141-4/+16
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* | Added support for verilog === operatorClifford Wolf2013-05-071-0/+2
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* | Added tcl "yosys -import" commandClifford Wolf2013-05-021-3/+29
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* | Improved/simplified TCL bindingsClifford Wolf2013-05-013-40/+57
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* | Added support for const cell inputs in techmapClifford Wolf2013-04-271-6/+28
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* | Fixed README for new show command behavior (svg vs. ps)Clifford Wolf2013-04-271-2/+6
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* | Added "flatten" passClifford Wolf2013-04-261-1/+41
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* | Fixed handling of positional module parametersClifford Wolf2013-04-261-6/+4
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* | Fixed hierarchy pass for hierarchies of parametric modulesClifford Wolf2013-04-261-0/+1
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* | Only use sha1 checksums for names of parametric modules when the verbose ↵Clifford Wolf2013-04-261-9/+20
| | | | | | | | form is to long
* | Fixed "show -format ..." command line parsingClifford Wolf2013-04-151-1/+1
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* | Added "submod -name ..." supportClifford Wolf2013-04-151-40/+96
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* | Fixed a bug in AST frontend for cases with non-blocking assigned variables ↵Clifford Wolf2013-04-132-4/+23
| | | | | | | | as case values
* | Fixed a bug in opt_const when optimizing 1-bit compares with constantsClifford Wolf2013-04-131-2/+4
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* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2013-04-071-8/+40
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| * \ Merge pull request #5 from hansiglaser/masterClifford Wolf2013-04-051-6/+23
| |\ \ | | | | | | | | fsm_export: optionally use binary state encoding as state names instead of s0, s1, ...
| | * | fsm_export: optionally use binary state encoding as state names instead ofJohann Glaser2013-04-051-6/+23
| | | | | | | | | | | | | | | | s0, s1, ...
| * | | Merge pull request #4 from hansiglaser/masterClifford Wolf2013-04-051-5/+20
| |\| | | | | | | | | | fsm_export: specify KISS filename on command line
| | * | fsm_export: specify KISS filename on command lineJohann Glaser2013-04-051-5/+20
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* / / Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.vClifford Wolf2013-04-071-4/+4
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* | Fixed/improved handling of colored wires in show commandClifford Wolf2013-04-011-2/+2
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* | Added support for @<set-name> in expand select ops (%x, %ci, %co)Clifford Wolf2013-04-011-2/+12
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* | Removed 4096 bytes limit for size of command from script fileClifford Wolf2013-04-011-3/+20
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* | Added -color <color> <selection> option to show commandClifford Wolf2013-04-014-22/+101
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* | Fixed "select" for "%%" stmt with emty stackClifford Wolf2013-03-311-1/+2
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* | Added "script" commandClifford Wolf2013-03-311-0/+16
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* | Now only use value from "initial" when no matching "always" block is foundClifford Wolf2013-03-315-21/+32
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* | Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)Clifford Wolf2013-03-315-3/+15
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* | Added test cases from 2012 paper on comparison of foss verilog synthesis toolsClifford Wolf2013-03-316-0/+111
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* | Added k68 (m68k compatible cpu) test case from verilatorClifford Wolf2013-03-313-0/+61
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* | Improved opt_share for reduce cellsClifford Wolf2013-03-293-3/+32
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