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| author | Clifford Wolf <clifford@clifford.at> | 2013-05-23 11:19:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-05-23 11:19:33 +0200 |
| commit | e04d88cf226df77aab81c05d232250f50b1ea5bc (patch) | |
| tree | b0a2876709988d805792ec694e189637ecda40ec | |
| parent | 6a38e767ba9abb68f1a066f381147fc609d496df (diff) | |
| download | yosys-e04d88cf226df77aab81c05d232250f50b1ea5bc.tar.gz yosys-e04d88cf226df77aab81c05d232250f50b1ea5bc.tar.bz2 yosys-e04d88cf226df77aab81c05d232250f50b1ea5bc.zip | |
Added missing newline to some error messages
| -rw-r--r-- | passes/techmap/techmap.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index 732bd5cb9..4e1afe92a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -73,10 +73,10 @@ static void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name)); if (tpl->memories.size() != 0) - log_error("Technology map yielded memories -> this is not supported."); + log_error("Technology map yielded memories -> this is not supported.\n"); if (tpl->processes.size() != 0) - log_error("Technology map yielded processes -> this is not supported."); + log_error("Technology map yielded processes -> this is not supported.\n"); for (auto &it : tpl->wires) { RTLIL::Wire *w = new RTLIL::Wire(*it.second); |