diff options
| author | Clifford Wolf <clifford@clifford.at> | 2013-04-07 16:42:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-04-07 16:42:29 +0200 |
| commit | 32dbf7752d5ae41966bf19773bf8561b538fe8f0 (patch) | |
| tree | bd388e8adfa4d4ccaef087048e9a1022fc60fe52 | |
| parent | af4444e5b96e133f0c64b931759acf5df86475ad (diff) | |
| download | yosys-32dbf7752d5ae41966bf19773bf8561b538fe8f0.tar.gz yosys-32dbf7752d5ae41966bf19773bf8561b538fe8f0.tar.bz2 yosys-32dbf7752d5ae41966bf19773bf8561b538fe8f0.zip | |
Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v
| -rw-r--r-- | techlibs/simlib.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/simlib.v b/techlibs/simlib.v index 8675a4d0f..ff988cbe5 100644 --- a/techlibs/simlib.v +++ b/techlibs/simlib.v @@ -799,8 +799,8 @@ parameter MEMID = ""; parameter ABITS = 8; parameter WIDTH = 8; -parameter RD_CLK_ENABLE = 0; -parameter RD_CLK_POLARITY = 0; +parameter CLK_ENABLE = 0; +parameter CLK_POLARITY = 0; input CLK; input [ABITS-1:0] ADDR; @@ -821,8 +821,8 @@ parameter MEMID = ""; parameter ABITS = 8; parameter WIDTH = 8; -parameter RD_CLK_ENABLE = 0; -parameter RD_CLK_POLARITY = 0; +parameter CLK_ENABLE = 0; +parameter CLK_POLARITY = 0; input CLK, EN; input [ABITS-1:0] ADDR; |