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| * CodingReadme updateClifford Wolf2015-02-081-0/+1
| * Fixed bug in "show -format .."Clifford Wolf2015-02-081-1/+1
| * Added new APIs to changelogClifford Wolf2015-02-081-0/+1
| * Fixed eval_select_op() apiClifford Wolf2015-02-082-2/+2
| * Added eval_select_args() and eval_select_op()Clifford Wolf2015-02-082-4/+29
| * Minor "make vgtest" changesClifford Wolf2015-02-082-2/+6
| * Various ModIndex improvementsClifford Wolf2015-02-081-13/+54
| * Added Yosys 0.5 ChangelogClifford Wolf2015-02-081-4/+46
| * Various updates to CodingReadmeClifford Wolf2015-02-081-10/+13
| * Added equiv_addClifford Wolf2015-02-082-0/+90
| * Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-081-0/+14
| * Fixed a bug with autowire bit sizeClifford Wolf2015-02-081-9/+3
| * fixed typoClifford Wolf2015-02-081-1/+1
| * Added "yosys-config --build modname.so cppsources.."Clifford Wolf2015-02-081-2/+12
| * Added SigSpec::has_const()Clifford Wolf2015-02-082-0/+13
| * Cleanup in add_share_file make macroClifford Wolf2015-02-081-3/+3
| * Removed "make mklibyosys"Clifford Wolf2015-02-071-14/+0
| * Improved building of pluginsClifford Wolf2015-02-072-3/+36
| * Added "make uninstall"Clifford Wolf2015-02-071-0/+4
| * Added cell->known(), cell->input(portname), cell->output(portname)Clifford Wolf2015-02-072-0/+39
| * Added "select -read"Clifford Wolf2015-02-061-5/+39
| * Auto-detect TCL versionClifford Wolf2015-02-052-2/+2
| * Added onehot attributeClifford Wolf2015-02-043-0/+19
| * Fixed opt_clean performance bugClifford Wolf2015-02-041-26/+26
| * Disabled (unused) Xilinx tristate buffersClifford Wolf2015-02-041-6/+6
| * Using design->selected_modules() in opt_*Clifford Wolf2015-02-035-36/+20
| * Skip blackbox modules in design->selected_modules()Clifford Wolf2015-02-031-3/+5
| * Added "yosys -L logfile"Clifford Wolf2015-02-031-1/+7
| * Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-02-012-3/+3
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| | * Merge pull request #48 from rubund/masterClifford Wolf2015-02-012-3/+3
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| | | * Fixed typos found by lintianRuben Undheim2015-02-012-3/+3
| * | | no support for 6-series xilinx devicesClifford Wolf2015-02-011-1/+1
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| * / Improved performance in equiv_simpleClifford Wolf2015-02-012-23/+73
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| * Removed old XST-based xilinx examplesClifford Wolf2015-02-0111-208/+0
| * Added Xilinx example for Basys3 boardClifford Wolf2015-02-019-1/+84
| * Added EDIF backend support for multi-bit cell portsClifford Wolf2015-02-011-11/+10
| * Added missing ports and parameters to xilinx bramsClifford Wolf2015-02-011-4/+18
| * Added "make mklibyosys", some minor API changesClifford Wolf2015-02-017-11/+70
| * Minor README changesClifford Wolf2015-02-011-3/+2
| * Removed TODO list from README fileClifford Wolf2015-02-011-30/+0
| * Added yosys_banner(), Updated Copyright rangeClifford Wolf2015-02-014-26/+31
| * Added <algorithm> include to hashlib.hClifford Wolf2015-02-011-0/+1
| * Using selections in "ls" commandClifford Wolf2015-02-011-34/+30
| * Shorter "dump" optionsClifford Wolf2015-01-311-4/+4
| * Bugfix in opt_const $eq -> buffer codeClifford Wolf2015-01-311-4/+4
| * Log msg changeClifford Wolf2015-01-311-1/+1
| * Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")Clifford Wolf2015-01-311-12/+31
| * Added "equiv_induct -undef"Clifford Wolf2015-01-312-6/+51
| * Added "equiv_simple -undef"Clifford Wolf2015-01-312-17/+61
| * Added "equiv_make -blacklist <file> -encfile <file>"Clifford Wolf2015-01-314-5/+189
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