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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-08 00:58:03 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-08 00:58:03 +0100 |
| commit | 234a45a3d5d4b36e12d40033d58ac2ac3250fa27 (patch) | |
| tree | bf6b840792d86256e0a0e570b134b32cae2955b0 | |
| parent | c8305e3a6d1e195391eb6962aac5bf7e1c548b5d (diff) | |
| download | yosys-234a45a3d5d4b36e12d40033d58ac2ac3250fa27.tar.gz yosys-234a45a3d5d4b36e12d40033d58ac2ac3250fa27.tar.bz2 yosys-234a45a3d5d4b36e12d40033d58ac2ac3250fa27.zip | |
Ignore explicit assignments to constants in HDL code
| -rw-r--r-- | frontends/ast/genrtlil.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index f48101934..71248663e 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1296,6 +1296,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) { RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec right = children[1]->genWidthRTLIL(left.size()); + if (left.has_const()) { + RTLIL::SigSpec new_left, new_right; + for (int i = 0; i < GetSize(left); i++) + if (left[i].wire) { + new_left.append(left[i]); + new_right.append(right[i]); + } + log_warning("Ignoring assignment to constant bits at %s:%d:\n" + " old assignment: %s = %s\n new assignment: %s = %s.\n", + filename.c_str(), linenum, log_signal(left), log_signal(right), + log_signal(new_left), log_signal(new_right)); + left = new_left; + right = new_right; + } current_module->connect(RTLIL::SigSig(left, right)); } break; |