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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-01 00:48:22 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-01 00:48:22 +0100 |
| commit | b59bb8a528bf4fcf764016e61bf6a59239f35b86 (patch) | |
| tree | 030832a1f99dea0528a1644cdf441125143ac12e | |
| parent | 9948ff2d8a96a3c48188650601a2a75dec4a573d (diff) | |
| download | yosys-b59bb8a528bf4fcf764016e61bf6a59239f35b86.tar.gz yosys-b59bb8a528bf4fcf764016e61bf6a59239f35b86.tar.bz2 yosys-b59bb8a528bf4fcf764016e61bf6a59239f35b86.zip | |
Removed TODO list from README file
| -rw-r--r-- | README | 30 |
1 files changed, 0 insertions, 30 deletions
@@ -366,33 +366,3 @@ from SystemVerilog: - The keywords "always_comb", "always_ff" and "always_latch", "logic" and "bit" are supported. - -Roadmap / Large-scale TODOs -=========================== - -- Technology mapping for real-world applications - - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) - -- Implement SAT-based formal equivialence checker - - Write equiv pass based on hint-based register mapping - -- Re-implement Verilog frontend (far future) - - cleaner (easier to use, harder to use wrong) AST format - - pipeline of well structured AST transformations - - true contextual name lookup - - -Other Unsorted TODOs -==================== - -- Implement missing Verilog 2005 features: - - - Support for real (float) const. expressions and parameters - - Ignore what needs to be ignored (e.g. drive and charge strengths) - - Check standard vs. implementation to identify missing features - -- Miscellaneous TODO items: - - - Add brief source code documentation to most passes and kernel code - - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - |