| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | Bump version | Yosys Bot | 2020-11-03 | 1 | -1/+1 |
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| * | Merge pull request #2426 from whitequark/cxxrtl-auto-top | whitequark | 2020-11-02 | 1 | -7/+26 |
| |\ | | | | | cxxrtl: run `hierarchy -auto-top` if no top module is present | ||||
| | * | cxxrtl: run `hierarchy -auto-top` if no top module is present. | whitequark | 2020-11-02 | 1 | -7/+26 |
| |/ | | | | | | | | | | | | In most cases, a CXXRTL simulation would use a top module, either because this module serves as an entry point to the CXXRTL C API, or because the outputs of a top module are unbuffered, improving performance. Taking this into account, the CXXRTL backend now runs `hierarchy -auto-top` if there is no top module. For the few cases where this behavior is unwanted, it now accepts a `-nohierarchy` option. Fixes #2373. | ||||
| * | Bump version | Yosys Bot | 2020-11-02 | 1 | -1/+1 |
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| * | Merge pull request #2425 from whitequark/cxxrtl-meminit-constness | whitequark | 2020-11-01 | 1 | -2/+4 |
| |\ | | | | | cxxrtl: don't assert on non-constant $meminit inputs | ||||
| | * | cxxrtl: don't assert on non-constant $meminit inputs. | whitequark | 2020-11-01 | 1 | -2/+4 |
| |/ | | | | Fixes #2129. | ||||
| * | Merge pull request #2424 from whitequark/cxxrtl-multiple-drivers | whitequark | 2020-11-01 | 1 | -0/+2 |
| |\ | | | | | cxxrtl: don't assert on wires with multiple drivers | ||||
| | * | cxxrtl: don't assert on wires with multiple drivers. | whitequark | 2020-11-01 | 1 | -0/+2 |
| |/ | | | | Fixes #2374. | ||||
| * | Bump version | Yosys Bot | 2020-11-01 | 1 | -1/+1 |
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| * | Merge pull request #2416 from QuantamHD/master | whitequark | 2020-10-31 | 1 | -1/+6 |
| |\ | | | | | Adds support for defining abc location at runtime | ||||
| | * | This patch adds support for defining the ABC location at runtime instead of ↵ | Ethan Mahintorabi | 2020-10-28 | 1 | -1/+6 |
| | | | | | | | | | | | | | at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase. This change should be backwards compatible with the existing behavior. | ||||
| * | | Bump version | Yosys Bot | 2020-10-31 | 1 | -1/+1 |
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| * | | Update verific version | Miodrag Milanovic | 2020-10-30 | 1 | -1/+1 |
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| * | Bump version | Yosys Bot | 2020-10-25 | 1 | -1/+1 |
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| * | xilinx: Fix attributes_test.ys | Marcelina Kościelnicka | 2020-10-24 | 1 | -4/+2 |
| | | | | | | | | | | | This test pretty much passes by accident — the `prep` command runs memory_collect without memory_dff first, which prevents merging read register into the memory, and thus blocks block RAM inference for a reason completely unrelated to the attribute. The attribute setting didn't actually work because it was set on the containing module instead of the actual memory. | ||||
| * | Bump version | Yosys Bot | 2020-10-23 | 1 | -1/+1 |
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| * | nexus: Add make_transp to BRAMs | David Shah | 2020-10-22 | 1 | -0/+3 |
| | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | Merge pull request #2403 from nakengelhardt/sim_timescale | N. Engelhardt | 2020-10-22 | 1 | -0/+21 |
| |\ | | | | | sim -vcd: add date, version, and option for timescale | ||||
| | * | use strftime instead of put_time for gcc 4.8 compatibility | N. Engelhardt | 2020-10-21 | 1 | -4/+5 |
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| | * | wild guessing at the problem because it builds fine on my machines | N. Engelhardt | 2020-10-16 | 1 | -0/+3 |
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| | * | sim -vcd: add date, version, and option for timescale | N. Engelhardt | 2020-10-16 | 1 | -0/+17 |
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| * | | memory_dff: Fix needlessly duplicating enable bits. | Marcelina Kościelnicka | 2020-10-22 | 2 | -0/+32 |
| | | | | | | | | | | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409. | ||||
| * | | Bump version | Yosys Bot | 2020-10-22 | 1 | -1/+1 |
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| * | | btor: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -93/+102 |
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| * | | smt2: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -186/+244 |
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| * | | verilog_backend: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -274/+251 |
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| * | | sim: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -103/+90 |
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| * | | clk2fflogic: Use Mem helper. | Marcelina Kościelnicka | 2020-10-21 | 1 | -68/+45 |
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| * | | opt_mem: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -81/+6 |
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| * | | memory_bram: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -121/+90 |
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| * | | memory_map: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -138/+81 |
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| * | | memory_unpack: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -106/+10 |
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| * | | memory_collect: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -223/+9 |
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| * | | memory_nordff: Use Mem helpers. | Marcelina Kościelnicka | 2020-10-21 | 1 | -63/+9 |
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| * | | Add new helper structures to represent memories. | Marcelina Kościelnicka | 2020-10-21 | 3 | -1/+516 |
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| * | | Bump version | Yosys Bot | 2020-10-21 | 1 | -1/+1 |
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| * | | Merge pull request #2405 from byuccl/fix_xilinx_cells | clairexen | 2020-10-20 | 1 | -2/+2 |
| |\ \ | | | | | | | xilinx/cells_sim.v: Move signal declaration to before first use | ||||
| | * | | Move signal declarations to before first use | Jeff Goeders | 2020-10-19 | 1 | -2/+2 |
| | | | | | | | | | | | | | Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com> | ||||
| * | | | Merge pull request #2404 from YosysHQ/claire/fixrpcargs | clairexen | 2020-10-20 | 1 | -1/+2 |
| |\ \ \ | | | | | | | | | Fix argument handling in connect_rpc | ||||
| | * | | | Fix argument handling in connect_rpc | Claire Xenia Wolf | 2020-10-19 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com> | ||||
| * | | | | Bump version | Yosys Bot | 2020-10-20 | 1 | -1/+1 |
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| * | | | Merge pull request #2397 from daveshah1/nexus | Miodrag Milanović | 2020-10-19 | 30 | -0/+12528 |
| |\ \ \ | |_|/ |/| | | synth_nexus: Initial implementation | ||||
| | * | | synth_nexus: Initial implementation | David Shah | 2020-10-15 | 30 | -0/+12528 |
| | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| * | | | Bump version | Yosys Bot | 2020-10-16 | 1 | -1/+1 |
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| * | | | Merge pull request #2398 from jakobwenzel/smtbmc-escape | clairexen | 2020-10-15 | 1 | -11/+29 |
| |\ \ \ | | | | | | | | | smtbmc: escape identifiers in verilog testbench | ||||
| | * | | | smtbmc: escape identifiers in verilog testbench | Jakob Wenzel | 2020-10-06 | 1 | -11/+29 |
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| * | | | | Bump version | Yosys Bot | 2020-10-13 | 1 | -1/+1 |
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| * | | | | extend verific library API for formal apps and generators | Miodrag Milanovic | 2020-10-12 | 1 | -15/+83 |
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| * | | | | Bump version | Yosys Bot | 2020-10-09 | 1 | -1/+1 |
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| * | | | | opt_clean: Better memory handling. | Marcelina Kościelnicka | 2020-10-08 | 2 | -8/+94 |
| |/ / / | | | | | | | | | | | | | | | | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved. | ||||
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