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| author | clairexen <claire@symbioticeda.com> | 2020-10-20 17:11:36 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-10-20 17:11:36 +0200 |
| commit | e919d0c1255cda47fa5835ad468266621cab0ecf (patch) | |
| tree | 4df3626e791a0368cd103469941701aaac3ce672 | |
| parent | 099d0c2a8ae3c4ef43703afcabf8ce98be124d95 (diff) | |
| parent | 8be56960a26081ab57542d71fb78be594b9e014f (diff) | |
| download | yosys-e919d0c1255cda47fa5835ad468266621cab0ecf.tar.gz yosys-e919d0c1255cda47fa5835ad468266621cab0ecf.tar.bz2 yosys-e919d0c1255cda47fa5835ad468266621cab0ecf.zip | |
Merge pull request #2405 from byuccl/fix_xilinx_cells
xilinx/cells_sim.v: Move signal declaration to before first use
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 40804c367..4162160bb 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -2335,6 +2335,8 @@ parameter integer PREG = 1; // The multiplier. wire signed [35:0] P_MULT; +wire signed [17:0] A_MULT; +wire signed [17:0] B_MULT; assign P_MULT = A_MULT * B_MULT; // The cascade output. @@ -2373,8 +2375,6 @@ always @(posedge CLK) begin end // The register enables. -wire signed [17:0] A_MULT; -wire signed [17:0] B_MULT; assign A_MULT = (AREG == 1) ? A_REG : A; assign B_MULT = (BREG == 1) ? B_REG : B_MUX; assign P = (PREG == 1) ? P_REG : P_MULT; |