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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-17 22:21:05 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-10-21 17:51:20 +0200 |
commit | 06141db233b9c8e2d4eaee678f8c43a1d7648bc7 (patch) | |
tree | 220842322f822a70abb98446d5cfda8afdb9729c | |
parent | 21896e2a028ce742725f94336c1f6507382ee428 (diff) | |
download | yosys-06141db233b9c8e2d4eaee678f8c43a1d7648bc7.tar.gz yosys-06141db233b9c8e2d4eaee678f8c43a1d7648bc7.tar.bz2 yosys-06141db233b9c8e2d4eaee678f8c43a1d7648bc7.zip |
opt_mem: Use Mem helpers.
-rw-r--r-- | passes/opt/opt_mem.cc | 87 |
1 files changed, 6 insertions, 81 deletions
diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc index 24df1356b..49a0ac51a 100644 --- a/passes/opt/opt_mem.cc +++ b/passes/opt/opt_mem.cc @@ -19,82 +19,11 @@ #include "kernel/yosys.h" #include "kernel/sigtools.h" +#include "kernel/mem.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -struct OptMemWorker -{ - RTLIL::Design *design; - RTLIL::Module *module; - SigMap sigmap; - bool restart; - - dict<IdString, vector<IdString>> memrd, memwr, meminit; - pool<IdString> remove_mem, remove_cells; - - OptMemWorker(RTLIL::Module *module) : design(module->design), module(module), sigmap(module), restart(false) - { - for (auto &it : module->memories) - { - memrd[it.first]; - memwr[it.first]; - meminit[it.first]; - } - - for (auto cell : module->cells()) - { - if (cell->type == ID($memrd)) { - IdString id = cell->getParam(ID::MEMID).decode_string(); - memrd.at(id).push_back(cell->name); - } - - if (cell->type == ID($memwr)) { - IdString id = cell->getParam(ID::MEMID).decode_string(); - memwr.at(id).push_back(cell->name); - } - - if (cell->type == ID($meminit)) { - IdString id = cell->getParam(ID::MEMID).decode_string(); - meminit.at(id).push_back(cell->name); - } - } - } - - ~OptMemWorker() - { - for (auto it : remove_mem) - { - for (auto cell_name : memrd[it]) - module->remove(module->cell(cell_name)); - for (auto cell_name : memwr[it]) - module->remove(module->cell(cell_name)); - for (auto cell_name : meminit[it]) - module->remove(module->cell(cell_name)); - - delete module->memories.at(it); - module->memories.erase(it); - } - - for (auto cell_name : remove_cells) - module->remove(module->cell(cell_name)); - } - - int run(RTLIL::Memory *mem) - { - if (restart || remove_mem.count(mem->name)) - return 0; - - if (memwr.at(mem->name).empty() && meminit.at(mem->name).empty()) { - log("Removing memory %s.%s with no write ports or init data.\n", log_id(module), log_id(mem)); - remove_mem.insert(mem->name); - return 1; - } - - return 0; - } -}; - struct OptMemPass : public Pass { OptMemPass() : Pass("opt_mem", "optimize memories") { } void help() override @@ -122,15 +51,11 @@ struct OptMemPass : public Pass { int total_count = 0; for (auto module : design->selected_modules()) { - while (1) { - int cnt = 0; - OptMemWorker worker(module); - for (auto &it : module->memories) - if (module->selected(it.second)) - cnt += worker.run(it.second); - if (!cnt && !worker.restart) - break; - total_count += cnt; + for (auto &mem : Mem::get_selected_memories(module)) { + if (mem.wr_ports.empty() && mem.inits.empty()) { + mem.remove(); + total_count++; + } } } |