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* | Improvements in cellaigs.cc and "json -aig"Clifford Wolf2015-06-112-10/+215
* | AigMaker refactoringClifford Wolf2015-06-104-78/+153
* | Added "json -aig"Clifford Wolf2015-06-103-9/+76
* | Renamed "aig" to "aigmap"Clifford Wolf2015-06-103-10/+10
* | Fixed cellaigs port extendingClifford Wolf2015-06-103-3/+11
* | Added "aig" passClifford Wolf2015-06-093-16/+291
* | synth_ice40 now flattens by defaultClifford Wolf2015-06-091-4/+8
* | Added cellaigs APIClifford Wolf2015-06-094-2/+173
* | Merge clock inverters in memory_dffClifford Wolf2015-06-091-16/+37
* | Merge branch 'verilog-backend-memV2' of github.com:wluker/yosysClifford Wolf2015-06-091-54/+110
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| * | $mem cell in verilog backend : grouped writes by clockluke whittlesey2015-06-082-58/+110
| * | Bug fix in $mem verilog backend + changed tests/bram flow of make test.luke whittlesey2015-06-042-16/+20
* | | Fixed "avail_parameters" handling in module clone/copyClifford Wolf2015-06-081-0/+2
* | | Added log_dump() support for IdStringsClifford Wolf2015-06-082-0/+5
* | | Fixed handling of parameters with reversed rangeClifford Wolf2015-06-081-1/+1
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* | Added opt_share -share_allClifford Wolf2015-05-312-16/+32
* | Added iCE40 PLL cellsClifford Wolf2015-05-311-0/+168
* | Added liberty dont_use support to dfflibmapClifford Wolf2015-05-311-0/+4
* | Fixed signedness of genvar expressionsClifford Wolf2015-05-291-2/+2
* | Added output args to synth_ice40Clifford Wolf2015-05-262-2/+37
* | Improvements in BLIF front-endClifford Wolf2015-05-242-4/+51
* | improved ice40 SB_IO sim modelClifford Wolf2015-05-231-16/+9
* | Improved "flatten" handlings of inout portsClifford Wolf2015-05-231-2/+26
* | Added simple $dlatch support to opt_rmdffClifford Wolf2015-05-231-0/+35
* | Added ice40 SB_IO sim modelClifford Wolf2015-05-231-1/+46
* | Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2015-05-221-19/+23
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| * | Some fixes for $mem in verilog back-endClifford Wolf2015-05-201-19/+23
* | | preserve used $-wires with init attribute in opt_cleanClifford Wolf2015-05-221-1/+1
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* | bugfix in blif front-endClifford Wolf2015-05-182-6/+6
* | added vloghtb test_febe.shClifford Wolf2015-05-172-0/+49
* | Improved .latch support in BLIF front-endClifford Wolf2015-05-171-3/+30
* | Added read_blif commandClifford Wolf2015-05-172-1/+33
* | Generalized blifparse APIClifford Wolf2015-05-173-21/+31
* | abc/blifparse files reorganizationClifford Wolf2015-05-177-8/+9
* | Verific build fixesClifford Wolf2015-05-175-7/+7
* | Added .barbuf support to abc BLIF parserClifford Wolf2015-05-131-0/+20
* | changed file() to open() in python scriptsClifford Wolf2015-05-114-11/+11
* | Merge pull request #63 from wluker/verilog-backend-memClifford Wolf2015-05-111-1/+2
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| * | Fixed bug in $mem cell verilog code generation.luke whittlesey2015-05-111-11/+12
* | | Disabled broken $mem support in verilog backendClifford Wolf2015-05-101-11/+11
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* | Merge pull request #62 from wluker/verilog-backend-memClifford Wolf2015-05-101-1/+164
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| * | Made changes recommended by Clifford Wolf ...luke whittlesey2015-05-101-22/+11
| * | Verilog backend for $mem cells should now be able to handle differentluke whittlesey2015-05-081-50/+105
| * | Added support for $mem cells in the verilog backend.luke whittlesey2015-05-071-1/+120
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* | Fixed memory_unpack for initialized memoriesClifford Wolf2015-04-291-0/+17
* | Preserve important attributes in splitnetsClifford Wolf2015-04-291-0/+13
* | Added $eq/$neq -> $logic_not/$reduce_bool optimizationClifford Wolf2015-04-294-1/+38
* | ice40_opt bugfixClifford Wolf2015-04-272-6/+4
* | iCE40: SB_CARRY const fold -> unmap SB_LUTClifford Wolf2015-04-271-3/+44
* | Added simplemap $lut supportClifford Wolf2015-04-273-8/+27
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