diff options
| author | Clifford Wolf <clifford@clifford.at> | 2015-05-22 08:20:29 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-05-22 08:20:29 +0200 |
| commit | e122c2644e4bbcb9384c7f0b65c69cc9671698dd (patch) | |
| tree | aaff4a959e8aee755e6def866e9cc0f13b1bfa2b | |
| parent | 6061b7bd58c2f528f33d1f3859f99a5d0babca21 (diff) | |
| download | yosys-e122c2644e4bbcb9384c7f0b65c69cc9671698dd.tar.gz yosys-e122c2644e4bbcb9384c7f0b65c69cc9671698dd.tar.bz2 yosys-e122c2644e4bbcb9384c7f0b65c69cc9671698dd.zip | |
preserve used $-wires with init attribute in opt_clean
| -rw-r--r-- | passes/opt/opt_clean.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 9d2a262a1..a34da781a 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -216,7 +216,7 @@ void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos std::vector<RTLIL::Wire*> maybe_del_wires; for (auto wire : module->wires()) { - if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep")) { + if ((!purge_mode && check_public_name(wire->name)) || wire->port_id != 0 || wire->get_bool_attribute("\\keep") || wire->attributes.count("\\init")) { RTLIL::SigSpec s1 = RTLIL::SigSpec(wire), s2 = s1; assign_map.apply(s2); if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) { |