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| author | Clifford Wolf <clifford@clifford.at> | 2015-05-26 17:04:37 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-05-26 17:08:53 +0200 |
| commit | c329233f0de691d818cc8b1aff3dd23cebf38949 (patch) | |
| tree | 4eb622a5d7b0d355807043d647c7ccff60261b43 | |
| parent | 08a4af3cde27acb57085d2eac5f897310d98a06e (diff) | |
| download | yosys-c329233f0de691d818cc8b1aff3dd23cebf38949.tar.gz yosys-c329233f0de691d818cc8b1aff3dd23cebf38949.tar.bz2 yosys-c329233f0de691d818cc8b1aff3dd23cebf38949.zip | |
Added output args to synth_ice40
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 35 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 4 |
2 files changed, 37 insertions, 2 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index e23290319..e1cfa977b 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -47,6 +47,14 @@ struct SynthIce40Pass : public Pass { log(" -top <module>\n"); log(" use the specified module as top module (default='top')\n"); log("\n"); + log(" -blif <file>\n"); + log(" write the design to the specified BLIF file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -edif <file>\n"); + log(" write the design to the specified edif file. writing of an output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); log(" from label is synonymous to 'begin', and empty to label is\n"); @@ -111,11 +119,18 @@ struct SynthIce40Pass : public Pass { log(" stat\n"); log(" check -noinit\n"); log("\n"); + log(" blif:\n"); + log(" write_blif -gates -attr -param <file-name>\n"); + log("\n"); + log(" edif:\n"); + log(" write_edif <file-name>\n"); + log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { std::string top_opt = "-auto-top"; std::string run_from, run_to; + std::string blif_file, edif_file; bool nocarry = false; bool nobram = false; bool flatten = false; @@ -128,6 +143,14 @@ struct SynthIce40Pass : public Pass { top_opt = "-top " + args[++argidx]; continue; } + if (args[argidx] == "-blif" && argidx+1 < args.size()) { + blif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx+1 < args.size()) { + edif_file = args[++argidx]; + continue; + } if (args[argidx] == "-run" && argidx+1 < args.size()) { size_t pos = args[argidx+1].find(':'); if (pos == std::string::npos) @@ -230,6 +253,18 @@ struct SynthIce40Pass : public Pass { Pass::call(design, "check -noinit"); } + if (check_label(active, run_from, run_to, "blif")) + { + if (!blif_file.empty()) + Pass::call(design, stringf("write_blif -gates -attr -param %s", blif_file.c_str())); + } + + if (check_label(active, run_from, run_to, "edif")) + { + if (!edif_file.empty()) + Pass::call(design, stringf("write_edif %s", edif_file.c_str())); + } + log_pop(); } } SynthIce40Pass; diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 0e2fdac73..8ef0fae12 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -110,8 +110,8 @@ struct SynthXilinxPass : public Pass { log(" stat\n"); log(" check -noinit\n"); log("\n"); - log(" edif:\n"); - log(" write_edif synth.edif\n"); + log(" edif: (only if -edif)\n"); + log(" write_edif <file-name>\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) |