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| * | | | | | | | | | | | | | | | | Fix SRL16/32 techmap off-by-oneEddie Hung2019-02-281-18/+24
| * | | | | | | | | | | | | | | | | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-282-24/+29
| * | | | | | | | | | | | | | | | | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-282-22/+19
| * | | | | | | | | | | | | | | | | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
| * | | | | | | | | | | | | | | | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32Eddie Hung2019-02-281-0/+71
* | | | | | | | | | | | | | | | | | Add MUXCY and XORCY to cells_box.vEddie Hung2019-04-162-0/+15
* | | | | | | | | | | | | | | | | | Fix wire numberingEddie Hung2019-04-161-1/+2
* | | | | | | | | | | | | | | | | | Do not put constants into output_bitsEddie Hung2019-04-161-2/+2
* | | | | | | | | | | | | | | | | | Remove write_verilog callEddie Hung2019-04-161-1/+1
* | | | | | | | | | | | | | | | | | Fix spacingEddie Hung2019-04-162-2/+2
* | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-162-3/+1
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| * | | | | | | | | | | | | | | | | Re-enable partsel.v testEddie Hung2019-04-161-1/+0
| * | | | | | | | | | | | | | | | | abc9 to call "setundef -zero" behaving as for abcEddie Hung2019-04-161-0/+3
* | | | | | | | | | | | | | | | | | NULL check before useEddie Hung2019-04-161-1/+1
* | | | | | | | | | | | | | | | | | WIP for box supportEddie Hung2019-04-161-36/+93
* | | | | | | | | | | | | | | | | | ABC to read_box before reading netlistEddie Hung2019-04-161-1/+3
* | | | | | | | | | | | | | | | | | Make cells.box whiteboxes not blackboxesEddie Hung2019-04-161-2/+2
* | | | | | | | | | | | | | | | | | read_verilog cells_box.v before techmapEddie Hung2019-04-161-1/+1
* | | | | | | | | | | | | | | | | | synth_xilinx: before abc read +/xilinx/cells_box.vEddie Hung2019-04-161-0/+1
* | | | | | | | | | | | | | | | | | Add +/xilinx/cells_box.v containing models for ABC boxesEddie Hung2019-04-162-0/+11
* | | | | | | | | | | | | | | | | | For 'stat' do not count modules with abc_box_idEddie Hung2019-04-161-0/+3
* | | | | | | | | | | | | | | | | | Do not call abc on modules with abc_box_id attrEddie Hung2019-04-161-0/+3
* | | | | | | | | | | | | | | | | | Revert "Add abc_box_id attribute to MUXF7/F8 cells"Eddie Hung2019-04-161-2/+0
* | | | | | | | | | | | | | | | | | Use abc_box_idEddie Hung2019-04-151-2/+1
* | | | | | | | | | | | | | | | | | Check abc_box_id attrEddie Hung2019-04-151-1/+16
* | | | | | | | | | | | | | | | | | Add abc_box_id attribute to MUXF7/F8 cellsEddie Hung2019-04-151-0/+2
* | | | | | | | | | | | | | | | | | Merge branch 'xaig' into xc7muxEddie Hung2019-04-159-100/+246
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| * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-153-6/+5
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| | * | | | | | | | | | | | | | | | Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatchEddie Hung2019-04-152-4/+3
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| | | * | | | | | | | | | | | | | | | Revert "Recognise default entry in case even if all cases covered (fix for #9...Eddie Hung2019-04-152-4/+3
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| | * | | | | | | | | | | | | | | | Merge pull request #936 from YosysHQ/README-fix-quotesEddie Hung2019-04-151-2/+2
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| | | * | | | | | | | | | | | | | | README: fix some incorrect quoting.whitequark2019-04-151-2/+2
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| * | | | | | | | | | | | | | | | Forgot backslashesEddie Hung2019-04-121-1/+1
| * | | | | | | | | | | | | | | | Handle __dummy_o__ and __const[01]__ in read_aiger not abcEddie Hung2019-04-122-18/+8
| * | | | | | | | | | | | | | | | abc to ignore __dummy_o__ and __const[01]__ when re-integratingEddie Hung2019-04-121-6/+20
| * | | | | | | | | | | | | | | | Output __const0__ and __const1__ CIsEddie Hung2019-04-121-7/+10
| * | | | | | | | | | | | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-121-12/+32
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| | * | | | | | | | | | | | | | | | Fix inout handling for -map optionEddie Hung2019-04-121-10/+30
| * | | | | | | | | | | | | | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-04-120-0/+0
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| | * | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| * | | | | | | | | | | | | | | | | Use -map instead of -symbols for aigerEddie Hung2019-04-121-2/+3
| * | | | | | | | | | | | | | | | | ci_bits and co_bits now a list, order is important for ABCEddie Hung2019-04-121-24/+34
| * | | | | | | | | | | | | | | | | Also cope with duplicated CIsEddie Hung2019-04-121-5/+23
| * | | | | | | | | | | | | | | | | WIPEddie Hung2019-04-121-14/+68
| * | | | | | | | | | | | | | | | | Comment outEddie Hung2019-04-121-1/+1
| * | | | | | | | | | | | | | | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress optEddie Hung2019-04-122-1/+14
| * | | | | | | | | | | | | | | | | Cope with an output having same name as an input (i.e. CO)Eddie Hung2019-04-121-5/+23
| * | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-127-50/+76
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| | * | | | | | | | | | | | | | | Merge pull request #928 from litghost/add_xc7_sim_modelsEddie Hung2019-04-123-41/+60
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| | | * | | | | | | | | | | | | | | Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.Keith Rothman2019-04-123-52/+14
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-22 03:46:29 +0000