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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 09:32:29 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 09:32:29 -0800 |
| commit | c9ab18889a63f74534c6fe9184ccb32e3661ab90 (patch) | |
| tree | 005a535f7f84c9daa93bdfeec7b8cec809bc82e8 | |
| parent | c29f0c5048fce87258eb4a4b204b6584efe0170c (diff) | |
| download | yosys-c9ab18889a63f74534c6fe9184ccb32e3661ab90.tar.gz yosys-c9ab18889a63f74534c6fe9184ccb32e3661ab90.tar.bz2 yosys-c9ab18889a63f74534c6fe9184ccb32e3661ab90.zip | |
synth_xilinx to now have shregmap call after dff2dffe
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6c11d885d..afd868743 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -103,6 +103,7 @@ struct SynthXilinxPass : public Pass log(" memory_map\n"); log(" dffsr2dff\n"); log(" dff2dffe\n"); + log(" shregmap -init\n"); log(" opt -full\n"); log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n"); log(" opt -fast\n"); @@ -222,6 +223,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); + Pass::call(design, "shregmap -init"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); |