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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 14:53:01 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 14:53:01 -0700 |
| commit | ece5c3ab38023abc251828b9379ea4eca9573abc (patch) | |
| tree | fdce92e50ebe7ecaf21397fcc0c49f107466963d | |
| parent | 43cd047fb9d73c43f8fe2c35c457cfa8fc3523ec (diff) | |
| download | yosys-ece5c3ab38023abc251828b9379ea4eca9573abc.tar.gz yosys-ece5c3ab38023abc251828b9379ea4eca9573abc.tar.bz2 yosys-ece5c3ab38023abc251828b9379ea4eca9573abc.zip | |
Fix wire numbering
| -rw-r--r-- | backends/aiger/xaiger.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 7c7697874..66ab3878e 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -589,11 +589,12 @@ struct XAigerWriter if (cell->input(c.first)) { box_inputs += c.second.size(); if (holes_cell) { - holes_wire = holes_module->wire(stringf("\\i%d", num_inputs++)); + holes_wire = holes_module->wire(stringf("\\i%d", num_inputs)); if (!holes_wire) { holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs)); holes_wire->port_input = true; } + ++num_inputs; holes_cell->setPort(c.first, holes_wire); } } |