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* Remove executable flag from filesMiodrag Milanovic2020-02-155-0/+0
* Add comment for macOS dependency installMiodrag Milanović2020-02-151-1/+1
* Revert "abc9: fix abc9_arrival for flops"Eddie Hung2020-02-142-36/+4
* Merge pull request #1701 from nakengelhardt/rpc-testMiodrag Milanović2020-02-143-7/+7
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| * make rpc frontend unix socket test less fragileN. Engelhardt2020-02-133-7/+7
* | Merge pull request #1700 from YosysHQ/eddie/abc9_fixesEddie Hung2020-02-133-29/+51
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| * | write_xaiger: default value for abc9_initEddie Hung2020-02-131-1/+1
| * | abc9: fix abc9_arrival for flopsEddie Hung2020-02-132-4/+36
| * | abc9: deprecate abc9_ff.init wire for (* abc9_init *) attrEddie Hung2020-02-132-24/+14
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* | Merge pull request #1699 from YosysHQ/eddie/fix_iopad_initEddie Hung2020-02-132-0/+46
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| * Fine tune #1699 testsEddie Hung2020-02-131-14/+14
| * iopadmap: fixes as suggested by @mwkmwkmwkEddie Hung2020-02-131-19/+11
| * iopadmap: move \init attributes from outpad output to its inputEddie Hung2020-02-132-3/+57
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* Merge pull request #1694 from rqou/json_compat_fixClaire Wolf2020-02-131-3/+3
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| * json: Change compat mode to directly emit ints <= 32 bitsR. Ou2020-02-091-3/+3
* | Merge pull request #1679 from thasti/delay-parsingN. Engelhardt2020-02-132-2/+7
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| * | add testcase for #1614Stefan Biereigel2020-02-031-0/+5
| * | correct wire declaration grammar for #1614Stefan Biereigel2020-02-031-2/+2
* | | abc9: cleanupEddie Hung2020-02-102-41/+41
* | | Merge pull request #1670 from rodrigomelo9/masterEddie Hung2020-02-107-3/+152
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| * | | Added 'set -e' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-061-0/+20
| * | | Modified $readmem[hb] to use '\' or '/' according the OSRodrigo Alejandro Melo2020-02-061-1/+6
| * | | Merge branch 'master' into masterRodrigo A. Melo2020-02-0310-4/+367
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| * \ \ \ Merge branch 'master' of https://github.com/YosysHQ/yosysRodrigo Alejandro Melo2020-02-0312-112/+369
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| * | | | | Replaced strlen by GetSize into simplify.ccRodrigo Alejandro Melo2020-02-031-2/+2
| * | | | | Removed 'synth' into tests/memfile/run-test.shRodrigo Alejandro Melo2020-02-021-8/+8
| * | | | | Added content1.dat into tests/memfileRodrigo Alejandro Melo2020-02-022-21/+81
| * | | | | Removed a line jump into the CHANGELOGRodrigo Alejandro Melo2020-02-011-3/+2
| * | | | | Added tests/memfile to 'make test' with an extra testcaseRodrigo Alejandro Melo2020-02-012-16/+11
| * | | | | Added a test for the Memory Content File inclusion using $readmembRodrigo Alejandro Melo2020-02-013-0/+63
| * | | | | Fixed a bug in the new feature of $readmem[hb] when an empty string is providedRodrigo Alejandro Melo2020-02-011-1/+1
| * | | | | Modified the new search for files of $readmem[hb] to be backward compatibleRodrigo Alejandro Melo2020-01-311-3/+7
| * | | | | $readmem[hb] file inclusion is now relative to the Verilog fileRodrigo Alejandro Melo2020-01-312-2/+4
* | | | | | Merge pull request #1669 from thasti/pyosys-attrsN. Engelhardt2020-02-101-2/+38
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| * | | | | | remove namespace mention from inheritance informationStefan Biereigel2020-02-031-1/+1
| * | | | | | expose polymorphism through python wrappersStefan Biereigel2020-02-031-2/+8
| * | | | | | add inheritance for pywrap generatorsStefan Biereigel2020-01-301-0/+30
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* | | | | | Merge pull request #1695 from whitequark/manual-explain-wire-upto-offsetwhitequark2020-02-091-0/+7
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| * | | | | manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
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* | | | | Remove unnecessary commaEddie Hung2020-02-071-3/+2
* | | | | Merge pull request #1687 from YosysHQ/eddie/fix_ystestsEddie Hung2020-02-072-9/+7
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| * | | | | techmap: fix shiftx2mux decompositionEddie Hung2020-02-071-8/+6
| * | | | | Fix misc.abc9.abc9_abc9_lutsEddie Hung2020-02-071-1/+1
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* | | | | xilinx: Add support for LUT RAM on LUT4-based devices.Marcin Kościelnicki2020-02-075-27/+42
* | | | | xilinx: Initial support for LUT4 devices.Marcin Kościelnicki2020-02-076-54/+235
* | | | | Merge pull request #1685 from dh73/gowinEddie Hung2020-02-061-1/+1
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| * | | | | Removing cells_sim.v from bram techmap passDiego H2020-02-061-1/+1
* | | | | | Merge pull request #1683 from whitequark/write_verilog-memattrswhitequark2020-02-071-0/+1
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| * | | | | | write_verilog: dump $mem cell attributes.whitequark2020-02-061-0/+1
* | | | | | | xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.Marcin Kościelnicki2020-02-0711-1/+370
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