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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-07 12:32:08 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-07 12:32:08 -0800 |
| commit | be8bc63f8443ea0aa2261bbbe4f30de476fa4a61 (patch) | |
| tree | 508316620c3d31e7fb8ea11eadf1fd667e9e63db | |
| parent | 89adef352fde57fa599d66fe404c3c2b9e607a7f (diff) | |
| parent | affae35847c45e708436b9142cfa7d7eb6b5aec6 (diff) | |
| download | yosys-be8bc63f8443ea0aa2261bbbe4f30de476fa4a61.tar.gz yosys-be8bc63f8443ea0aa2261bbbe4f30de476fa4a61.tar.bz2 yosys-be8bc63f8443ea0aa2261bbbe4f30de476fa4a61.zip | |
Merge pull request #1687 from YosysHQ/eddie/fix_ystests
Fix shiftx2mux, fix yosys-tests
| -rw-r--r-- | passes/techmap/abc9_exe.cc | 2 | ||||
| -rw-r--r-- | techlibs/common/techmap.v | 14 |
2 files changed, 7 insertions, 9 deletions
diff --git a/passes/techmap/abc9_exe.cc b/passes/techmap/abc9_exe.cc index 71221951c..d3db0065c 100644 --- a/passes/techmap/abc9_exe.cc +++ b/passes/techmap/abc9_exe.cc @@ -471,7 +471,7 @@ struct Abc9ExePass : public Pass { // handle -lut / -luts args if (!lut_arg.empty()) { string arg = lut_arg; - if (arg.find_first_not_of("0123456789:") == std::string::npos) { + if (arg.find_first_not_of("0123456789:,") == std::string::npos) { size_t pos = arg.find_first_of(':'); int lut_mode = 0, lut_mode2 = 0; if (pos != string::npos) { diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v index be6530eb4..ecf4d5dc5 100644 --- a/techlibs/common/techmap.v +++ b/techlibs/common/techmap.v @@ -149,16 +149,14 @@ module _90_shift_shiftx (A, B, Y); _TECHMAP_CONSTVAL_B_[CLOG2_Y_WIDTH-1:0] == {CLOG2_Y_WIDTH{1'b0}}) begin // Halve the size of $shift/$shiftx by $mux-ing A according to // the LSB of B, after discarding the zeroed bits - localparam len = 2**(B_WIDTH-1); localparam Y_WIDTH2 = 2**CLOG2_Y_WIDTH; - wire [len-1:0] T, F, AA; - wire [(A_WIDTH+Y_WIDTH2*2):0] Apad = {{Y_WIDTH2*2{extbit}}, A}; + localparam entries = (A_WIDTH+Y_WIDTH-1)/Y_WIDTH2; + localparam len = Y_WIDTH2 * ((entries+1)/2); + wire [len-1:0] AA; + wire [(A_WIDTH+Y_WIDTH2+Y_WIDTH-1)-1:0] Apad = {{(Y_WIDTH2+Y_WIDTH-1){extbit}}, A}; genvar i; - for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) begin - assign F[i/2 +: Y_WIDTH2] = A[i +: Y_WIDTH2]; - assign T[i/2 +: Y_WIDTH2] = Apad[i+Y_WIDTH2 +: Y_WIDTH2]; - assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? T[i/2 +: Y_WIDTH2] : F[i/2 +: Y_WIDTH2]; - end + for (i = 0; i < A_WIDTH; i=i+Y_WIDTH2*2) + assign AA[i/2 +: Y_WIDTH2] = B[CLOG2_Y_WIDTH] ? Apad[i+Y_WIDTH2 +: Y_WIDTH2] : Apad[i +: Y_WIDTH2]; wire [B_WIDTH-2:0] BB = {B[B_WIDTH-1:CLOG2_Y_WIDTH+1], {CLOG2_Y_WIDTH{1'b0}}}; if (_TECHMAP_CELLTYPE_ == "$shift") $shift #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(len), .B_WIDTH(B_WIDTH-1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(AA), .B(BB), .Y(Y)); |