| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | PI before CI | Eddie Hung | 2019-04-12 | 1 | -2/+2 |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-04-12 | 1 | -3/+9 |
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| | * | Merge pull request #933 from dh73/master | Clifford Wolf | 2019-04-12 | 1 | -3/+9 |
| | |\ | | | | | | | Fixing issues in CycloneV cell sim | ||||
| | | * | Fixing issues in CycloneV cell sim | Diego | 2019-04-11 | 1 | -3/+9 |
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| | * | | Merge pull request #932 from YosysHQ/eddie/fixdlatch | Clifford Wolf | 2019-04-12 | 2 | -3/+4 |
| | |\ \ | | |/ | |/| | Recognise default entry in case even if all cases covered (fix for #931) | ||||
| * | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux | Eddie Hung | 2019-04-11 | 1 | -1/+0 |
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| | * | | | More unused | Eddie Hung | 2019-04-11 | 1 | -1/+0 |
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| * | | | | Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux | Eddie Hung | 2019-04-11 | 6 | -8/+93 |
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| | * | | | Remove unused | Eddie Hung | 2019-04-11 | 1 | -1/+0 |
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| | * | | | Fixes | Eddie Hung | 2019-04-11 | 1 | -20/+16 |
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| | * | | | WIP | Eddie Hung | 2019-04-11 | 2 | -0/+89 |
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| | * | | | Spelling fixes | Eddie Hung | 2019-04-11 | 1 | -2/+2 |
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| | * | | Add default entry to testcase | Eddie Hung | 2019-04-11 | 1 | -2/+3 |
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| | * | | Recognise default entry in case even if all cases covered (#931) | Eddie Hung | 2019-04-11 | 1 | -1/+1 |
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| | * | Fix a few typos | Eddie Hung | 2019-04-08 | 1 | -3/+3 |
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| * | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 |
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| * | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 |
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| * | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 |
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| * | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 |
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| * | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 2 | -30/+35 |
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| * | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -1/+1 |
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| | * | | Add non-input bits driven by unrecognised cells as ci_bits | Eddie Hung | 2019-04-10 | 1 | -1/+1 |
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| * | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 |
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| * | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 |
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| * | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 |
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| * | | | Update doc for synth_xilinx | Eddie Hung | 2019-04-10 | 1 | -7/+8 |
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| * | | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-04-10 | 1 | -24/+21 |
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| | * | | parse_aiger() to rename all $lut cells after "clean" | Eddie Hung | 2019-04-10 | 1 | -24/+21 |
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| * | | | ff_map.v after abc | Eddie Hung | 2019-04-10 | 1 | -5/+5 |
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| * | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 |
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| * | | | Move map_cells to before map_luts | Eddie Hung | 2019-04-10 | 1 | -11/+12 |
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| * | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 |
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| * | | | Update LUT delays | Eddie Hung | 2019-04-10 | 1 | -11/+8 |
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| * | | | Add cells.lut to techlibs/xilinx/ | Eddie Hung | 2019-04-09 | 2 | -0/+16 |
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| * | | | synth_xilinx to call abc with -lut +/xilinx/cells.lut | Eddie Hung | 2019-04-09 | 1 | -2/+2 |
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| * | | | Add delays to cells.box | Eddie Hung | 2019-04-09 | 1 | -4/+12 |
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| * | | | Add "-lut <file>" support to abc9 | Eddie Hung | 2019-04-09 | 1 | -13/+31 |
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| * | | | synth_xilinx with abc9 to use -box | Eddie Hung | 2019-04-09 | 1 | -1/+4 |
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| * | | | Add techlibs/xilinx/cells.box | Eddie Hung | 2019-04-09 | 2 | -0/+6 |
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| * | | | Add "-box" option to abc9 | Eddie Hung | 2019-04-09 | 1 | -7/+22 |
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| * | | | Add 'setundef -zero' call prior to aigmap in abc9 | Eddie Hung | 2019-04-09 | 1 | -0/+4 |
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| * | | | Comment out | Eddie Hung | 2019-04-09 | 1 | -1/+1 |
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| * | | | Add support for synth_xilinx -abc9 and ignore abc9 -dress opt | Eddie Hung | 2019-04-09 | 2 | -1/+14 |
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| * | | More space fixing | Eddie Hung | 2019-04-08 | 1 | -2/+2 |
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| * | | Fix spacing | Eddie Hung | 2019-04-08 | 1 | -29/+29 |
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| * | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 115 | -710/+5842 |
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| | * | Merge pull request #919 from YosysHQ/multiport_transp | Clifford Wolf | 2019-04-08 | 1 | -1/+2 |
| | |\ | | | | | | | memory_bram: Fix multiport make_transp | ||||
| | | * | memory_bram: Fix multiport make_transp | David Shah | 2019-04-07 | 1 | -1/+2 |
| | |/ | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
| | * | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 5 | -3/+39 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Added missing argument checking to "mutate" command | Clifford Wolf | 2019-04-04 | 1 | -0/+32 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
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index : iCE40/yosys | |
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