| Commit message (Expand) | Author | Age | Files | Lines | ||
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| | | | * | | | | Fix #938 - Crash occurs in case when use write_firrtl command | Jim Lawson | 2019-05-01 | 3 | -4/+64 | |
| | | * | | | | | Fix floating point exception in qwp, fixes #923 | Clifford Wolf | 2019-05-01 | 1 | -1/+1 | |
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| | | * | | | | Fix segfault in wreduce | Clifford Wolf | 2019-04-30 | 1 | -0/+2 | |
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| | | * | | | Disabled "final loop assignment" feature | Clifford Wolf | 2019-04-30 | 1 | -0/+2 | |
| | | * | | | Merge pull request #972 from YosysHQ/clifford/fix968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 | |
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| | | | * | | | Add final loop variable assignment when unrolling for-loops, fixes #968 | Clifford Wolf | 2019-04-30 | 1 | -0/+7 | |
| | | * | | | | Merge pull request #966 from YosysHQ/clifford/fix956 | Clifford Wolf | 2019-04-30 | 3 | -3/+55 | |
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| | | | * | | | | Add handling of init attributes in "opt_expr -undriven" | Clifford Wolf | 2019-04-30 | 2 | -3/+42 | |
| | | | * | | | | Drive dangling wires with init attr with their init value, fixes #956 | Clifford Wolf | 2019-04-29 | 1 | -0/+13 | |
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| | | * | | | | Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx | Clifford Wolf | 2019-04-30 | 2 | -156/+101 | |
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| | | | * \ \ \ | Merge branch 'master' into eddie/refactor_synth_xilinx | Clifford Wolf | 2019-04-30 | 9 | -12/+40 | |
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| | | * | | | | | Merge pull request #973 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-30 | 3 | -4/+4 | |
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| | | | * \ \ \ \ | Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python... | Benedikt Tutzer | 2019-04-30 | 88 | -320/+2797 | |
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| | | | * | | | | | Cleaned up root directory | Benedikt Tutzer | 2019-04-30 | 3 | -4/+4 | |
| | | * | | | | | | Include filename in "Executing Verilog-2005 frontend" message, fixes #959 | Clifford Wolf | 2019-04-30 | 1 | -2/+2 | |
| | | * | | | | | | Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970 | Clifford Wolf | 2019-04-30 | 1 | -1/+1 | |
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| | | * | | | | | Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef | Clifford Wolf | 2019-04-29 | 1 | -3/+16 | |
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| | | | * | | | | | Add -undef option to equiv_opt, passed to equiv_induct | Eddie Hung | 2019-04-26 | 1 | -3/+16 | |
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| | | * | | | | | Merge pull request #967 from olegendo/depfile_esc_spaces | Clifford Wolf | 2019-04-29 | 3 | -2/+17 | |
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| | | | * | | | | fix codestyle formatting | Oleg Endo | 2019-04-29 | 3 | -14/+14 | |
| | | | * | | | | escape spaces with backslash when writing dep file | Oleg Endo | 2019-04-29 | 3 | -2/+17 | |
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| | | | | | * | Refactor synth_xilinx to auto-generate doc | Eddie Hung | 2019-04-26 | 1 | -153/+95 | |
| | | | | | * | Cleanup ice40 | Eddie Hung | 2019-04-26 | 1 | -4/+6 | |
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| | * | / | | Copy with 1'bx padding in $shiftx | Eddie Hung | 2019-04-28 | 1 | -1/+11 | |
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| | * / / | Where did this check come from!?! | Eddie Hung | 2019-04-26 | 1 | -1/+0 | |
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| | * | | Misspelling | Eddie Hung | 2019-04-25 | 1 | -1/+1 | |
| * | | | Add specify support to README | Clifford Wolf | 2019-04-23 | 1 | -0/+5 | |
| * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 4 | -13/+23 | |
| * | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 3 | -24/+24 | |
| * | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 9 | -6/+133 | |
| * | | | Preserve $specify[23] cells | Clifford Wolf | 2019-04-23 | 1 | -1/+1 | |
| * | | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 | |
| * | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 4 | -76/+76 | |
| * | | | Add $specify2/$specify3 support to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+47 | |
| * | | | Add support for $assert/$assume/$cover to write_verilog | Clifford Wolf | 2019-04-23 | 1 | -0/+10 | |
| * | | | Add CellTypes support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 2 | -0/+7 | |
| * | | | Add InternalCellChecker support for $specify2 and $specify3 | Clifford Wolf | 2019-04-23 | 1 | -7/+21 | |
| * | | | Checking and fixing specify cells in genRTLIL | Clifford Wolf | 2019-04-23 | 1 | -1/+15 | |
| * | | | Un-break default specify parser | Clifford Wolf | 2019-04-23 | 1 | -0/+1 | |
| * | | | Add specify parser | Clifford Wolf | 2019-04-23 | 5 | -33/+253 | |
| * | | | Add $specify2 and $specify3 cells to simlib | Clifford Wolf | 2019-04-23 | 1 | -0/+147 | |
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| * | | Merge pull request #957 from YosysHQ/oai4fix | Clifford Wolf | 2019-04-23 | 2 | -2/+2 | |
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| | * | | Fixes for OAI4 cell implementation | David Shah | 2019-04-23 | 2 | -2/+2 | |
| * | | | Format some names using inline code | Eddie Hung | 2019-04-23 | 1 | -2/+2 | |
| * | | | Fix spelling | Eddie Hung | 2019-04-23 | 1 | -1/+1 | |
| * | | | Remove some left-over log_dump() | Clifford Wolf | 2019-04-23 | 1 | -2/+0 | |
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| * | | Merge pull request #914 from YosysHQ/xc7srl | Eddie Hung | 2019-04-22 | 8 | -41/+382 | |
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| | * | | Update help message | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
| | * | | Move 'shregmap -tech xilinx' into map_cells | Eddie Hung | 2019-04-22 | 1 | -17/+20 | |
| | * | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-04-22 | 39 | -71/+3146 | |
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