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| * | | | | | | | | | | | | | | | | | Missing dep for test_pmgenEddie Hung2019-08-301-1/+1
| * | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-3061-367/+1765
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| * | | | | | | | | | | | | | | | | | | New pmgen requires explicit acceptEddie Hung2019-08-301-0/+2
| * | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-3070-562/+3098
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| | * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'master' into xc7dspDavid Shah2019-08-30190-4390/+8848
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| * | | | | | | | | | | | | | | | | | | | | Fix compile errorEddie Hung2019-08-202-8/+14
| * | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-20133-2288/+4174
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| * | | | | | | | | | | | | | | | | | | | | | xilinx_dsp to be sensitive to keep attributeEddie Hung2019-08-151-1/+14
| * | | | | | | | | | | | | | | | | | | | | | SimplifyEddie Hung2019-08-151-4/+2
| * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-1526-2242/+2277
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| * \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspEddie Hung2019-08-151-1/+5
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| | * | | | | | | | | | | | | | | | | | | | | | xilinx: Rework labels for faster Verilator testingDavid Shah2019-08-131-1/+5
| * | | | | | | | | | | | | | | | | | | | | | | ffH -> ffFJKGEddie Hung2019-08-152-15/+15
| * | | | | | | | | | | | | | | | | | | | | | | Fixes for reverting SigSpec helper functionsEddie Hung2019-08-142-10/+14
| * | | | | | | | | | | | | | | | | | | | | | | Perform C -> PCIN optimisation after pattern matcherEddie Hung2019-08-132-19/+72
| * | | | | | | | | | | | | | | | | | | | | | | Revert changes to RTLIL::SigSpec methodsEddie Hung2019-08-134-15/+36
| * | | | | | | | | | | | | | | | | | | | | | | Only swap ports if $mul and not $__mulEddie Hung2019-08-131-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | Add assign PCOUT = P to DSP48E1Eddie Hung2019-08-131-0/+2
| * | | | | | | | | | | | | | | | | | | | | | | Rename to XilinxDspPassEddie Hung2019-08-131-3/+3
| * | | | | | | | | | | | | | | | | | | | | | | Add DSP_A_MAXWIDTH_PARTIAL, refactorEddie Hung2019-08-132-145/+111
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| * | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-1276-551/+823
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| * | | | | | | | | | | | | | | | | | | | | | | Check nusers of DSP output, not whole flopEddie Hung2019-08-091-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | Improve ice40_dsp for non-fully-32-bit addersEddie Hung2019-08-091-3/+8
| * | | | | | | | | | | | | | | | | | | | | | | Add wreduce to synth_ice40 -dsp as wellEddie Hung2019-08-091-0/+1
| * | | | | | | | | | | | | | | | | | | | | | | Another filter -> ifEddie Hung2019-08-091-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | CleanupEddie Hung2019-08-092-18/+18
| * | | | | | | | | | | | | | | | | | | | | | | Pack partial-product adder DSP48E1 packingEddie Hung2019-08-093-10/+81
| * | | | | | | | | | | | | | | | | | | | | | | Fix checkEddie Hung2019-08-091-4/+6
| * | | | | | | | | | | | | | | | | | | | | | | Revert "Fix typo"Eddie Hung2019-08-091-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | Remove muxY and ffY for nowEddie Hung2019-08-082-35/+33
| * | | | | | | | | | | | | | | | | | | | | | | Remove signed from ports in +/xilinx/dsp_map.vEddie Hung2019-08-081-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | Rework ice40_dsp to map to SB_MAC16 earlier, and check before packingEddie Hung2019-08-086-40/+119
| * | | | | | | | | | | | | | | | | | | | | | | Combine techmap callsEddie Hung2019-08-081-2/+1
| * | | | | | | | | | | | | | | | | | | | | | | Only pack registers if {A,B,P}REG = 0, do not pack $dffeEddie Hung2019-08-081-3/+6
| * | | | | | | | | | | | | | | | | | | | | | | Move xilinx_dsp to before alumaccEddie Hung2019-08-081-6/+4
| * | | | | | | | | | | | | | | | | | | | | | | Disable $dffeEddie Hung2019-08-081-8/+8
| * | | | | | | | | | | | | | | | | | | | | | | INMODE is 5 bitsEddie Hung2019-08-081-1/+1
| * | | | | | | | | | | | | | | | | | | | | | | Fix copy-pasta typoEddie Hung2019-08-081-2/+2
| * | | | | | | | | | | | | | | | | | | | | | | ecp5: Replace '-dsp' with inverse logic '-nodsp' to match synth_xilinxDavid Shah2019-08-081-11/+11
| * | | | | | | | | | | | | | | | | | | | | | | ecp5: Bring up to date with mul2dsp changesDavid Shah2019-08-082-2/+10
| * | | | | | | | | | | | | | | | | | | | | | | Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dspDavid Shah2019-08-0852-562/+1165
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| | * | | | | | | | | | | | | | | | | | | | | | | Fix compile errorEddie Hung2019-08-071-2/+2
| | * | | | | | | | | | | | | | | | | | | | | | | Run "opt_expr -fine" instead of "wreduce" due to #1213Eddie Hung2019-08-071-2/+1
| | * | | | | | | | | | | | | | | | | | | | | | | Do not SigSpec::extract() beyond boundsEddie Hung2019-08-072-8/+10
| | * | | | | | | | | | | | | | | | | | | | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-08-0749-552/+1134
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| | * | | | | | | | | | | | | | | | | | | | | | | | Do not pack registers if (* keep *)Eddie Hung2019-08-071-0/+20
| * | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: add SIMD testsDavid Shah2019-08-083-3/+113
| * | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 model: test CE inputsDavid Shah2019-08-082-7/+17
| * | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: fix seq tests and add preadder testsDavid Shah2019-08-082-6/+91
| * | | | | | | | | | | | | | | | | | | | | | | | | DSP48E1 sim model: seq test workingDavid Shah2019-08-083-16/+60
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