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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 17:35:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-09 17:35:13 -0700 |
| commit | ab1d63a56595f11e10a5326bd83ce84d08badabe (patch) | |
| tree | 658768ff60f3cbeb0bab6c21d6df02c84276a5f9 | |
| parent | 3dd3ab98c2bb83f644fb1962d4de27a7416b0113 (diff) | |
| download | yosys-ab1d63a56595f11e10a5326bd83ce84d08badabe.tar.gz yosys-ab1d63a56595f11e10a5326bd83ce84d08badabe.tar.bz2 yosys-ab1d63a56595f11e10a5326bd83ce84d08badabe.zip | |
Check nusers of DSP output, not whole flop
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index f982a10cf..5dee36a11 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -112,8 +112,8 @@ endcode match ffP if param(dsp, \PREG).as_int() == 0 if !sigPused.empty() + if nusers(sigPused) == 2 select ffP->type.in($dff) - index <int> nusers(port(ffP, \D)) === 2 // DSP48E1 does not support clock inversion select param(ffP, \CLK_POLARITY).as_bool() filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused) |