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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 12:34:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 12:34:11 -0700 |
| commit | c320abc3f490b09b21804581c2b386c30d186a1e (patch) | |
| tree | afa5859f1a0d590d0fbc85949ca7f3f22b94acad | |
| parent | 96ee7b9cf7a6a9010bc820dc110bf945c35cb32e (diff) | |
| download | yosys-c320abc3f490b09b21804581c2b386c30d186a1e.tar.gz yosys-c320abc3f490b09b21804581c2b386c30d186a1e.tar.bz2 yosys-c320abc3f490b09b21804581c2b386c30d186a1e.zip | |
xilinx_dsp to be sensitive to keep attribute
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 1a3dcdcbb..7f1958d5d 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -29,8 +29,13 @@ match ffA endmatch code clock - if (ffA) + if (ffA) { clock = port(ffA, \CLK).as_bit(); + + for (auto b : port(ffA, \Q)) + if (b.wire->get_bool_attribute(\keep)) + reject; + } endcode match ffB @@ -45,6 +50,10 @@ endmatch code clock if (ffB) { + for (auto b : port(ffB, \Q)) + if (b.wire->get_bool_attribute(\keep)) + reject; + SigBit c = port(ffB, \CLK).as_bit(); if (clock != SigBit() && c != clock) @@ -156,6 +165,10 @@ code ffP clock // ffP = ffY; if (ffP) { + for (auto b : port(ffP, \Q)) + if (b.wire->get_bool_attribute(\keep)) + reject; + SigBit c = port(ffP, \CLK).as_bit(); if (clock != SigBit() && c != clock) |