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* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-2310-47/+124
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| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-2110-47/+124
* | int -> boolRobert Baruch2021-02-231-2/+2
* | Adds is_wire to SigBit and SigChunkRobert Baruch2021-02-231-0/+3
* | machxo2: Switch to LUT4 sim model which propagates less undefined/don't care ...William D. Jones2021-02-232-12/+6
* | machxo2: Update tribuf test to reflect active-low OE.William D. Jones2021-02-231-1/+2
* | machxo2: Add experimental status to help.William D. Jones2021-02-231-1/+1
* | machxo2: Add DCCA and DCMA blackbox primitives.William D. Jones2021-02-231-0/+17
* | machxo2: Fix reversed interpretation of REG_SD config bits.William D. Jones2021-02-231-2/+2
* | machxo2: Tristate is active-low.William D. Jones2021-02-232-5/+5
* | machxo2: Fix typos in FACADE_FF sim model.William D. Jones2021-02-231-5/+4
* | machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph.William D. Jones2021-02-232-6/+6
* | machxo2: Improve help_mode output in synth_machxo2.William D. Jones2021-02-231-5/+5
* | machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to...William D. Jones2021-02-232-1/+17
* | machxo2: Add missing OSCH oscillator primitive.William D. Jones2021-02-231-0/+10
* | machxo2: Add believed-to-be-correct tribuf test.William D. Jones2021-02-231-0/+9
* | machxo2: Add passing fsm, mux, and shifter tests.William D. Jones2021-02-233-0/+65
* | machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives.William D. Jones2021-02-233-3/+11
* | machxo2: Add -noiopad option to synth_machxo2.William D. Jones2021-02-231-2/+11
* | machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE.William D. Jones2021-02-231-1/+1
* | machxo2: Fix cells_sim typo where OFX1 was multiply-driven.William D. Jones2021-02-231-1/+1
* | machxo2: synth_machxo2 now maps ports to FACADE_IO.William D. Jones2021-02-232-0/+12
* | machxo2: Add initial value for Q in FACADE_FF.William D. Jones2021-02-231-0/+2
* | machxo2: Add FACADE_IO simulation model. More comments on models.William D. Jones2021-02-231-0/+25
* | machxo2: Add FACADE_SLICE simulation model.William D. Jones2021-02-231-0/+83
* | machxo2: Improve FACADE_FF simulation model.William D. Jones2021-02-231-12/+20
* | machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice.William D. Jones2021-02-232-4/+4
* | machxo2: Add dffe test.William D. Jones2021-02-231-0/+9
* | machxo2: Add dff.ys test, fix another cells_map.v typo.William D. Jones2021-02-232-1/+11
* | machxo2: Fix more oversights in machxo2 models. logic.ys test passes.William D. Jones2021-02-232-2/+6
* | machxo2: Add test/arch/machxo2 directory (test does not pass).William D. Jones2021-02-234-0/+15
* | machxo2: Fix typos. test/arch/run-test.sh passes.William D. Jones2021-02-232-2/+2
* | machxo2: Create basic techlibs and synth_machxo2 pass.William D. Jones2021-02-234-0/+320
* | frontend: json: parse negative valuesKarol Gugala2021-02-231-2/+10
* | assertpmux: Fix crash on unused $pmux output.Marcelina Koƛcielnicka2021-02-222-1/+19
* | Merge pull request #2586 from zachjs/tern-recursewhitequark2021-02-215-19/+195
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| * | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-125-19/+195
* | | Merge pull request #2591 from zachjs/verilog-preproc-unappliedwhitequark2021-02-213-1/+32
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| * | verilog: error on macro invocations with missing argument listsZachary Snow2021-02-193-1/+32
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* | Bump versionYosys Bot2021-02-181-1/+1
* | Merge pull request #2590 from RobertBaruch/fix_fast_sop_modeClaire Xen2021-02-171-1/+1
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| * | Fixes command line for abc pass in -fast -sop modeRobert Baruch2021-02-161-1/+1
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* | Bump versionYosys Bot2021-02-161-1/+1
* | Merge pull request #2574 from dh73/masterClaire Xen2021-02-151-0/+5
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| * | Accept disable case for SVA liveness properties.Diego H2021-02-041-0/+5
* | | Bump versionYosys Bot2021-02-131-1/+1
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* | Merge pull request #2585 from YosysHQ/dave/nexus-dotproductgatecat2021-02-121-0/+115
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| * | nexus: Add MULTADDSUB9X9WIDE sim modelDavid Shah2020-12-081-0/+115
* | | Ganulate Verific supportMiodrag Milanovic2021-02-121-8/+16
* | | Bump versionYosys Bot2021-02-121-1/+1