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| author | William D. Jones <thor0505@comcast.net> | 2021-01-30 23:55:00 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | 8b14152506cdae1f15a33189736cbd3388f3b345 (patch) | |
| tree | 73b4efde09895ac036d74c4dbdddbd4655239b8c | |
| parent | 8348c45e4f679b44b238c0f205e2e3815c909c38 (diff) | |
| download | yosys-8b14152506cdae1f15a33189736cbd3388f3b345.tar.gz yosys-8b14152506cdae1f15a33189736cbd3388f3b345.tar.bz2 yosys-8b14152506cdae1f15a33189736cbd3388f3b345.zip | |
machxo2: Fix typos in FACADE_FF sim model.
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 4e2a1bb6c..d2267e8fd 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -93,12 +93,11 @@ module FACADE_SLICE #( parameter LSRONMUX = "LSRMUX", parameter LUT0_INITVAL = 16'hFFFF, parameter LUT1_INITVAL = 16'hFFFF, + parameter REGMODE = "FF", parameter REG0_SD = "1", parameter REG1_SD = "1", parameter REG0_REGSET = "SET", parameter REG1_REGSET = "SET", - parameter REG0_REGMODE = "FF", - parameter REG1_REGMODE = "FF", parameter CCU2_INJECT1_0 = "YES", parameter CCU2_INJECT1_1 = "YES", parameter WREMUX = "INV" @@ -148,14 +147,14 @@ module FACADE_SLICE #( /* Reg can be fed either by M, or DI inputs; DI inputs muxes OFX and F outputs (in other words, feeds back into FACADE_SLICE). */ wire di0 = (REG0_SD == "1") ? M0 : DI0; - wire di1 = (REG0_SD == "1") ? M1 : DI1; + wire di1 = (REG1_SD == "1") ? M1 : DI1; FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG0_REGSET), - .REGMODE(REG0_REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0)); + .REGMODE(REGMODE)) REG_0 (.CLK(CLK), .DI(di0), .LSR(LSR), .CE(CE), .Q(Q0)); FACADE_FF#(.GSR(GSR), .CEMUX(CEMUX), .CLKMUX(CLKMUX), .LSRMUX(LSRMUX), .LSRONMUX(LSRONMUX), .SRMODE(SRMODE), .REGSET(REG1_REGSET), - .REGMODE(REG1_REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); + .REGMODE(REGMODE)) REG_1 (.CLK(CLK), .DI(di1), .LSR(LSR), .CE(CE), .Q(Q1)); endmodule module FACADE_IO #( |