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author | William D. Jones <thor0505@comcast.net> | 2020-11-20 18:16:45 -0500 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
commit | 19b043344c67a0ce5a8a14ef2960f366980c9873 (patch) | |
tree | f270ba513306dd8f2d99e36bdb048c56065b85c7 | |
parent | 84937e9689c6fddfc613356f9a629d7628939668 (diff) | |
download | yosys-19b043344c67a0ce5a8a14ef2960f366980c9873.tar.gz yosys-19b043344c67a0ce5a8a14ef2960f366980c9873.tar.bz2 yosys-19b043344c67a0ce5a8a14ef2960f366980c9873.zip |
machxo2: Add dffe test.
-rw-r--r-- | tests/arch/machxo2/dffs.ys | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys index 3e9f87fec..83a07cfee 100644 --- a/tests/arch/machxo2/dffs.ys +++ b/tests/arch/machxo2/dffs.ys @@ -8,3 +8,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:FACADE_FF select -assert-none t:FACADE_FF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 2 t:FACADE_FF t:LUT4 +select -assert-none t:FACADE_FF t:LUT4 %% t:* %D |