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* Merge pull request #1264 from YosysHQ/eddie/fix_1254Eddie Hung2019-08-081-0/+6
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| * opt_lut to ignore LUT cells, or those that drive bits, with (* keep *)Eddie Hung2019-08-071-0/+6
* | Merge pull request #1266 from YosysHQ/eddie/ice40_full_adderEddie Hung2019-08-0820-180/+180
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| * Remove dump callEddie Hung2019-08-071-1/+0
| * Move tests/various/opt* into tests/opt/Eddie Hung2019-08-075-1/+1
| * Remove ice40_unlut call, simply do equiv_opt on synth_ice40Eddie Hung2019-08-071-3/+1
| * Add testcase from removed opt_ff.{v,ys}Eddie Hung2019-08-071-0/+32
| * Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but runEddie Hung2019-08-072-24/+0
| * Allow whitebox modules to be overwrittenEddie Hung2019-08-072-3/+1
| * Update CHANGELOGEddie Hung2019-08-071-0/+2
| * Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPEREddie Hung2019-08-076-10/+128
| * Add testEddie Hung2019-08-071-1/+10
| * Remove ice40_unlutEddie Hung2019-08-072-107/+0
| * Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDEREddie Hung2019-08-073-39/+14
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* Merge pull request #1248 from YosysHQ/eddie/abc9_speedupEddie Hung2019-08-074-40/+48
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| * Add commentEddie Hung2019-08-071-2/+3
| * Revert "Add TODO"Eddie Hung2019-08-071-2/+0
| * Add TODOEddie Hung2019-08-071-0/+2
| * Compute box_lookup just onceEddie Hung2019-08-071-8/+24
| * Run "clean" on mapped_mod in its own designEddie Hung2019-08-072-24/+10
| * Run "clean -purge" on holes_module in its own designEddie Hung2019-08-071-6/+11
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* Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixesDavid Shah2019-08-071-101/+244
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| * ecp5: Make cells_sim.v consistent with nextpnrDavid Shah2019-08-071-101/+244
* | Merge pull request #1213 from YosysHQ/eddie/wreduce_addClifford Wolf2019-08-075-3/+226
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| * | Add signed opt_expr testsEddie Hung2019-08-061-0/+50
| * | Add signed testEddie Hung2019-08-061-0/+26
| * | Move LSB-trimming functionality from wreduce to opt_exprEddie Hung2019-08-062-23/+26
| * | Add SigSpec::extract_end() convenience functionEddie Hung2019-08-061-0/+1
| * | Restore original SigSpec::extract()Eddie Hung2019-08-061-1/+1
| * | Move LSB tests from wreduce to opt_exprEddie Hung2019-08-062-99/+101
| * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_addEddie Hung2019-08-0656-172/+763
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| * | | Try and fix againEddie Hung2019-07-191-5/+4
| * | | Add another testEddie Hung2019-07-191-1/+24
| * | | Do not access beyond boundsEddie Hung2019-07-191-1/+1
| * | | Add an SigSpec::at(offset, defval) convenience methodEddie Hung2019-07-191-0/+1
| * | | Wrap A and B in sigmapEddie Hung2019-07-191-2/+2
| * | | Remove "top" from messageEddie Hung2019-07-191-1/+1
| * | | Also optimise MSB of $subEddie Hung2019-07-191-3/+3
| * | | Add one more test with trimming Y_WIDTH of $subEddie Hung2019-07-191-11/+14
| * | | Be more explicitEddie Hung2019-07-191-6/+29
| * | | wreduce for $subEddie Hung2019-07-191-0/+23
| * | | Add tests for sub tooEddie Hung2019-07-191-1/+48
| * | | Add testEddie Hung2019-07-191-0/+22
| * | | SigSpec::extract to take negative lengthsEddie Hung2019-07-191-1/+1
* | | | Merge pull request #1240 from ucb-bar/firrtl-properties+pow+xnorClifford Wolf2019-08-072-94/+206
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| * | | | Support explicit FIRRTL properties for better accommodation of FIRRTL/Verilog...Jim Lawson2019-07-312-94/+206
| * | | | Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-3021-32/+164
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| * \ \ \ \ Merge remote-tracking branch 'upstream/master'Jim Lawson2019-07-24199-1214/+9423
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* | \ \ \ \ \ Merge pull request #1249 from mmicko/anlogic_fixClifford Wolf2019-08-071-16/+8
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| * | | | | | | anlogic : Fix alu mappingMiodrag Milanovic2019-08-031-16/+8
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