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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:48:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 16:48:38 -0700 |
| commit | 4545bf482f029b7a49a7c2f88514b6c86ebf563f (patch) | |
| tree | 70c5b7771bae2505a8914a7ef71b0da643f6a2e7 | |
| parent | 9776084eda50060594c6609295c7aa540bb400e1 (diff) | |
| download | yosys-4545bf482f029b7a49a7c2f88514b6c86ebf563f.tar.gz yosys-4545bf482f029b7a49a7c2f88514b6c86ebf563f.tar.bz2 yosys-4545bf482f029b7a49a7c2f88514b6c86ebf563f.zip | |
Remove tests/opt/opt_ff.{v,ys} as they don't seem to do anything but run
| -rw-r--r-- | tests/opt/opt_ff.v | 21 | ||||
| -rw-r--r-- | tests/opt/opt_ff.ys | 3 |
2 files changed, 0 insertions, 24 deletions
diff --git a/tests/opt/opt_ff.v b/tests/opt/opt_ff.v deleted file mode 100644 index a01b64b61..000000000 --- a/tests/opt/opt_ff.v +++ /dev/null @@ -1,21 +0,0 @@ -module top( - input clk, - input rst, - input [2:0] a, - output [1:0] b -); - reg [2:0] b_reg; - initial begin - b_reg <= 3'b0; - end - - assign b = b_reg[1:0]; - always @(posedge clk or posedge rst) begin - if(rst) begin - b_reg <= 3'b0; - end else begin - b_reg <= a; - end - end -endmodule - diff --git a/tests/opt/opt_ff.ys b/tests/opt/opt_ff.ys deleted file mode 100644 index 704c7acf3..000000000 --- a/tests/opt/opt_ff.ys +++ /dev/null @@ -1,3 +0,0 @@ -read_verilog opt_ff.v -synth_ice40 -ice40_unlut |