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Add timescale and generated-by header to yosys-smtbmc MkVcd
Clifford Wolf
2019-06-16
1
-0
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+2
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-18
1
-29
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+27
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Really permute Xilinx LUT mappings as default LUT6.I5:A6
Eddie Hung
2019-06-18
1
-16
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+16
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Revert "Fix (do not) permute LUT inputs, but permute mux selects"
Eddie Hung
2019-06-18
1
-33
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+31
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-18
2
-37
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+37
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Clean up
Eddie Hung
2019-06-18
1
-6
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+4
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Fix (do not) permute LUT inputs, but permute mux selects
Eddie Hung
2019-06-18
1
-31
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+33
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-9
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+8
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Fix copy-pasta issue
Eddie Hung
2019-06-17
1
-9
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+8
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
2
-33
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+59
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Permute INIT for +/xilinx/lut_map.v
Eddie Hung
2019-06-17
1
-32
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+58
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Simplify comment
Eddie Hung
2019-06-17
1
-1
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+1
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-5
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+5
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Update LUT7/8 delays to take account for [ABC]OUTMUX delay
Eddie Hung
2019-06-17
1
-5
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+5
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-1
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+1
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&scorr before &sweep, remove &retime as recommended
Eddie Hung
2019-06-17
1
-1
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+1
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-3
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+4
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Copy not move parameters/attributes
Eddie Hung
2019-06-17
1
-3
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+4
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
3
-27
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+37
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Fix leak removing cells during ABC integration; also preserve attr
Eddie Hung
2019-06-17
3
-27
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+37
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-17
1
-1
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+1
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Try -W 300
Eddie Hung
2019-06-17
1
-1
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+2
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Re-enable &dc2
Eddie Hung
2019-06-17
1
-1
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+1
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Try -W 300
Eddie Hung
2019-06-16
1
-1
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+2
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-16
3
-299
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+33
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Cleanup
Eddie Hung
2019-06-16
3
-299
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+33
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-15
1
-2
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+2
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Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
Eddie Hung
2019-06-15
1
-2
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+2
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-14
1
-1
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+3
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Leave breadcrumb behind
Eddie Hung
2019-06-14
1
-0
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+2
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Remove redundant condition
Eddie Hung
2019-06-14
1
-1
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+1
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Revert "Cleanup/optimise toposort in write_xaiger"
Eddie Hung
2019-06-14
1
-44
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+40
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Revert "Cleanup/optimise toposort in write_xaiger"
Eddie Hung
2019-06-14
1
-44
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+40
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-14
2
-11
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+16
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Update comment
Eddie Hung
2019-06-14
1
-1
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+2
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Check that whiteboxes are synthesisable
Eddie Hung
2019-06-14
1
-4
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+8
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Get rid of compiler warnings
Eddie Hung
2019-06-14
2
-7
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+7
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Update CHANGELOG
Eddie Hung
2019-06-14
1
-2
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+3
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Revert "Remove wide mux inference"
Eddie Hung
2019-06-14
5
-3
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+195
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Merge branch 'xaig' into xc7mux
Eddie Hung
2019-06-14
37
-1745
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+867
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As per @daveshah1 remove async DFF timing from xilinx
Eddie Hung
2019-06-14
1
-2
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+2
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Cover __APPLE__ too for little to big endian
Eddie Hung
2019-06-14
2
-8
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+16
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Update abc9 -D doc
Eddie Hung
2019-06-14
1
-1
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+2
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Enable "abc9 -D <num>" for timing-driven synthesis
Eddie Hung
2019-06-14
1
-9
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+9
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Further cleanup based on @daveshah1
Eddie Hung
2019-06-14
4
-47
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+47
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Resolve comments from @daveshah1
Eddie Hung
2019-06-14
3
-17
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+11
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Add XC7_WIRE_DELAY macro to synth_xilinx.cc
Eddie Hung
2019-06-14
1
-1
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+3
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Update delays based on SymbiFlow/prjxray-db
Eddie Hung
2019-06-14
1
-12
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+13
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Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}
Eddie Hung
2019-06-14
4
-3
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+3
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Comment out dist RAM boxing on ECP5 for now
Eddie Hung
2019-06-14
1
-1
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+1
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