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authorEddie Hung <eddie@fpgeh.com>2019-06-15 05:45:16 -0700
committerEddie Hung <eddie@fpgeh.com>2019-06-15 05:45:16 -0700
commitbf312043d47c5ca99e26e25d153b49b3d3603ea4 (patch)
tree983b84cd12ff3195255146ead0454776a9ebd390
parent7ff8330d1e159173f9ed3494b85b83cb97208ab5 (diff)
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Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O
-rw-r--r--techlibs/xilinx/abc_xc7.lut4
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_xc7.lut b/techlibs/xilinx/abc_xc7.lut
index 2e6906945..ceb27c659 100644
--- a/techlibs/xilinx/abc_xc7.lut
+++ b/techlibs/xilinx/abc_xc7.lut
@@ -9,7 +9,7 @@
5 3 127 238 407 472 631
6 5 127 238 407 472 631 642
# F7AMUX + F7BMUX / 2
-7 10 286 413 524 693 758 917 928
+7 10 286 335 446 615 680 839 850
# F8MUX
# F8MUX+F7MUX
-8 20 273 559 686 797 966 1031 1190 1201
+8 20 273 390 439 550 719 784 943 954