diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 13:34:40 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 13:34:40 -0700 |
| commit | 7ff8330d1e159173f9ed3494b85b83cb97208ab5 (patch) | |
| tree | 30775bab66b8927c2188ab59580f8cdd84663f80 | |
| parent | 46e69ee934a6a954b73bb7a5669b6ee6d3047247 (diff) | |
| download | yosys-7ff8330d1e159173f9ed3494b85b83cb97208ab5.tar.gz yosys-7ff8330d1e159173f9ed3494b85b83cb97208ab5.tar.bz2 yosys-7ff8330d1e159173f9ed3494b85b83cb97208ab5.zip | |
Leave breadcrumb behind
| -rw-r--r-- | backends/aiger/xaiger.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index 4d8bb7f00..df970e341 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -185,6 +185,8 @@ struct XAigerWriter if (!bit.wire->port_input) unused_bits.erase(bit); + // TODO: Speed up toposort -- ultimately we care about + // box ordering, but not individual AIG cells dict<SigBit, pool<IdString>> bit_drivers, bit_users; TopoSort<IdString, RTLIL::sort_by_id_str> toposort; bool abc_box_seen = false; |