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| * | | | | Use new port/param overload in pmgEddie Hung2019-09-204-22/+22
| * | | | | Output pattern matcher items as log_debug()Eddie Hung2019-09-202-31/+27
| * | | | | OPMODE is port not paramEddie Hung2019-09-201-7/+6
| * | | | | Merge remote-tracking branch 'origin/master' into xc7dspEddie Hung2019-09-204-18/+50
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| * | | | | | Do not run xilinx_dsp_cascadeAB for nowEddie Hung2019-09-201-1/+2
| * | | | | | WIP for xiinx_dsp_cascadeABEddie Hung2019-09-201-3/+499
| * | | | | | Run until convergenceEddie Hung2019-09-201-3/+9
| * | | | | | Cleanup ice40_dsp.pmgEddie Hung2019-09-201-12/+6
| * | | | | | Cleanup xilinx_dspEddie Hung2019-09-201-1/+1
| * | | | | | More exceptionsEddie Hung2019-09-201-2/+2
| * | | | | | Fix signedness bugEddie Hung2019-09-201-2/+2
| * | | | | | Update docEddie Hung2019-09-201-2/+2
| * | | | | | Add a xilinx_dsp_cascade matcher for PCIN -> PCOUTEddie Hung2019-09-204-54/+105
| * | | | | | Add an overload for port/param with default valueEddie Hung2019-09-201-0/+8
| * | | | | | Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40Eddie Hung2019-09-202-3/+2
| * | | | | | Revert "Move mul2dsp before wreduce"Eddie Hung2019-09-201-4/+5
| * | | | | | Move mul2dsp before wreduceEddie Hung2019-09-201-5/+4
| * | | | | | Small cleanupEddie Hung2019-09-201-19/+18
| * | | | | | Disable support for SB_MAC16 reset since it is asyncEddie Hung2019-09-192-3/+7
| * | | | | | SB_MAC16 ffCD to not pack same as ffOEddie Hung2019-09-191-2/+2
| * | | | | | Add more complicated macc testcaseEddie Hung2019-09-192-5/+39
| * | | | | | ClarifyEddie Hung2019-09-191-1/+2
| * | | | | | Update doc for ice40_dspEddie Hung2019-09-191-1/+10
| * | | | | | Tidy up, fix undrivenEddie Hung2019-09-191-32/+34
| * | | | | | Add an indexEddie Hung2019-09-192-0/+3
| * | | | | | $__ABC_REG to have WIDTH parameterEddie Hung2019-09-192-17/+18
| * | | | | | Fix DSP48E1 timing by breaking P path if MREG or PREGEddie Hung2019-09-194-349/+363
| * | | | | | Revert "Different approach to timing"Eddie Hung2019-09-194-195/+405
| * | | | | | Different approach to timingEddie Hung2019-09-194-405/+195
| * | | | | | Fix width of DEddie Hung2019-09-191-1/+1
| * | | | | | Add mac.sh and macc_tb.v for testingEddie Hung2019-09-192-0/+99
| * | | | | | Suppress $anyseq warningsEddie Hung2019-09-191-15/+32
| * | | | | | Use ID() macroEddie Hung2019-09-192-210/+210
| * | | | | | Use (* techmap_autopurge *) to suppress techmap warningsEddie Hung2019-09-192-94/+99
| * | | | | | D is 25 bits not 24 bits wideEddie Hung2019-09-191-1/+1
| * | | | | | Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dspEddie Hung2019-09-1914-95/+723
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| * | | | | | | When two boxes connect to each other, need not be a (* keep *)Eddie Hung2019-09-191-6/+1
| * | | | | | | Re-enable sign extension for C inputEddie Hung2019-09-191-4/+4
| * | | | | | | synth_xilinx to infer DSPs for Y_WIDTH >= 9 and [AB]_WIDTH >= 2Eddie Hung2019-09-191-1/+4
| * | | | | | | Tidy up synth_ice40, only restrict DSP_B_MINWIDTH=2Eddie Hung2019-09-191-1/+3
| * | | | | | | Do not perform width-checks for DSP48E1 which is much more complicatedEddie Hung2019-09-191-11/+0
| * | | | | | | Remove TODO as check should not be necessaryEddie Hung2019-09-191-1/+0
| * | | | | | | Revert index to selectEddie Hung2019-09-191-1/+1
| * | | | | | | Cleanup xilinx_dsp tooEddie Hung2019-09-191-37/+28
| * | | | | | | Refactor ce{mux,pol} -> hold{mux,pol}Eddie Hung2019-09-192-77/+77
| * | | | | | | Add HOLD/RST support for SB_MAC16Eddie Hung2019-09-192-69/+116
| * | | | | | | Add support for SB_MAC16 CD and H registersEddie Hung2019-09-192-13/+73
| * | | | | | | Refactor ice40_dsp.pmgEddie Hung2019-09-192-194/+426
| * | | | | | | Add more entriesEddie Hung2019-09-191-0/+1
| * | | | | | | Format macc.vEddie Hung2019-09-191-8/+8