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authorEddie Hung <eddie@fpgeh.com>2019-09-19 12:00:39 -0700
committerEddie Hung <eddie@fpgeh.com>2019-09-19 12:00:39 -0700
commit0020a18929c30744eae4960ab97f6ebefc32a154 (patch)
tree8729b2485b98468a74b80e97972c4f63a7f7259f
parent65fa8adf6c834cc3c73300a19d4fe96c31b8d361 (diff)
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-rw-r--r--CHANGELOG1
1 files changed, 1 insertions, 0 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 8d7dd3e19..8ee73771f 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -41,6 +41,7 @@ Yosys 0.9 .. Yosys 0.9-dev
- Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass
- Added "-match-init" option to "dff2dffs" pass
- Added +/mul2dsp.v for decomposing wide multipliers to custom-sized ones
+ - Added "ice40_dsp" for Lattice iCE40 DSP packing
- Added "xilinx_dsp" for Xilinx DSP packing
- "synth_xilinx" to now infer DSP blocks (-nodsp to disable)
- "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental)