| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added emscripten (emcc) support to build system and some build fixes | Clifford Wolf | 2014-08-22 | 11 | -14/+101 |
| * | Added DPI-C documentation to README file | Clifford Wolf | 2014-08-22 | 1 | -0/+12 |
| * | Added support for non-standard <plugin>:<c_name> DPI syntax | Clifford Wolf | 2014-08-22 | 1 | -0/+12 |
| * | Archibald Rust and Clifford Wolf: ffi-based dpi_call() | Clifford Wolf | 2014-08-22 | 3 | -9/+93 |
| * | Added "plugin" command | Clifford Wolf | 2014-08-22 | 6 | -10/+136 |
| * | Updated ABC to 4d547a5e065b | Clifford Wolf | 2014-08-22 | 1 | -1/+1 |
| * | Cosmetic changes to FSM tests | Clifford Wolf | 2014-08-21 | 1 | -1/+1 |
| * | Fixed small memory leak in ast simplify | Clifford Wolf | 2014-08-21 | 1 | -3/+3 |
| * | Added support for DPI function with different names in C and Verilog | Clifford Wolf | 2014-08-21 | 3 | -9/+20 |
| * | Added AstNode::asInt() | Clifford Wolf | 2014-08-21 | 3 | -2/+24 |
| * | Fixed memory leak in DPI function calls | Clifford Wolf | 2014-08-21 | 1 | -0/+4 |
| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2014-08-21 | 2 | -63/+100 |
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| | * | Added mod->addGate() methods for new gate types | Clifford Wolf | 2014-08-19 | 2 | -63/+100 |
| * | | Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) | Clifford Wolf | 2014-08-21 | 8 | -3/+135 |
| * | | Added support for global tasks and functions | Clifford Wolf | 2014-08-21 | 3 | -27/+49 |
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| * | Using "via_celltype" in $mul carry-save-acc implementation | Clifford Wolf | 2014-08-18 | 1 | -34/+72 |
| * | Added "via_celltype" attribute on task/func | Clifford Wolf | 2014-08-18 | 3 | -18/+110 |
| * | Performance fix for new $__lcu techmap rule | Clifford Wolf | 2014-08-18 | 1 | -7/+5 |
| * | Replaced recursive lcu scheme with bk adder | Clifford Wolf | 2014-08-18 | 1 | -61/+31 |
| * | Added const folding of AST_CASE to AST simplifier | Clifford Wolf | 2014-08-18 | 3 | -1/+41 |
| * | Fixed proc_{self,share}_dirname error handling | Clifford Wolf | 2014-08-17 | 1 | -4/+2 |
| * | Makefile fixes | Clifford Wolf | 2014-08-17 | 1 | -1/+4 |
| * | Improved AST ProcessGenerator performance | Clifford Wolf | 2014-08-17 | 1 | -3/+3 |
| * | Improved sig.remove2() performance | Clifford Wolf | 2014-08-17 | 1 | -2/+11 |
| * | Use stackmap<> in AST ProcessGenerator | Clifford Wolf | 2014-08-17 | 3 | -24/+22 |
| * | Added stackmap<> container | Clifford Wolf | 2014-08-17 | 2 | -2/+109 |
| * | Renamed toposort.h to utils.h | Clifford Wolf | 2014-08-17 | 3 | -2/+2 |
| * | Added module->uniquify() | Clifford Wolf | 2014-08-16 | 5 | -15/+29 |
| * | Fixed AOI/OAI expr handling in verilog backend | Clifford Wolf | 2014-08-16 | 1 | -4/+4 |
| * | Multiply using a carry-save accumulator | Clifford Wolf | 2014-08-16 | 1 | -5/+45 |
| * | Added "test_cell -s <seed>" | Clifford Wolf | 2014-08-16 | 1 | -5/+17 |
| * | AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map | Clifford Wolf | 2014-08-16 | 1 | -41/+26 |
| * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $... | Clifford Wolf | 2014-08-16 | 8 | -48/+399 |
| * | Added CellTypes::cell_evaluable() | Clifford Wolf | 2014-08-16 | 1 | -31/+37 |
| * | Changes in techmap $__alu interface | Clifford Wolf | 2014-08-16 | 1 | -17/+17 |
| * | Added "opt -fast" | Clifford Wolf | 2014-08-16 | 1 | -19/+45 |
| * | Added log_spacer() | Clifford Wolf | 2014-08-16 | 3 | -2/+20 |
| * | Bugfix in iopadmap | Clifford Wolf | 2014-08-15 | 1 | -1/+3 |
| * | Renamed $lut ports to follow A-Y naming scheme | Clifford Wolf | 2014-08-15 | 6 | -39/+38 |
| * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 19 | -47/+47 |
| * | Removed old doc references to $safe_pmux | Clifford Wolf | 2014-08-15 | 2 | -5/+1 |
| * | More idstring sort_by_* helpers and fixed tpl ordering in techmap | Clifford Wolf | 2014-08-15 | 4 | -10/+22 |
| * | Added Frontend "+/" filename syntax for files from proc_share_dir | Clifford Wolf | 2014-08-15 | 1 | -1/+4 |
| * | document "techmap -map %<design-name>" | Clifford Wolf | 2014-08-15 | 1 | -0/+3 |
| * | Fixed bug in "read_verilog -ignore_redef" | Clifford Wolf | 2014-08-15 | 1 | -1/+1 |
| * | Added RTLIL::SigSpec::to_sigbit_map() | Clifford Wolf | 2014-08-14 | 3 | -11/+20 |
| * | Changed the AST genWidthRTLIL subst interface to use a std::map | Clifford Wolf | 2014-08-14 | 3 | -21/+31 |
| * | Added sig.{replace,remove,extract} variants for std::{map,set} pattern | Clifford Wolf | 2014-08-14 | 2 | -25/+64 |
| * | Fixed line numbers when using here-doc macros | Clifford Wolf | 2014-08-14 | 1 | -4/+9 |
| * | Fixed handling of task outputs | Clifford Wolf | 2014-08-14 | 1 | -2/+4 |
