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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-17 02:24:53 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-17 02:24:53 +0200 |
| commit | aa3a6663e2e9a63b88cfb1d008e3e246dc9fa677 (patch) | |
| tree | b4be7e1ba0c9ed5c4a3b3378535e43e7ebb19c97 | |
| parent | 64713647a966e8a14dff39f9ac18aafe9c882f46 (diff) | |
| download | yosys-aa3a6663e2e9a63b88cfb1d008e3e246dc9fa677.tar.gz yosys-aa3a6663e2e9a63b88cfb1d008e3e246dc9fa677.tar.bz2 yosys-aa3a6663e2e9a63b88cfb1d008e3e246dc9fa677.zip | |
Makefile fixes
| -rw-r--r-- | Makefile | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -80,7 +80,7 @@ LDLIBS += -l$(TCL_VERSION) endif ifeq ($(ENABLE_GPROF),1) -CXXFLAGS += -pg -fno-inline +CXXFLAGS += -pg LDFLAGS += -pg endif @@ -150,6 +150,7 @@ OBJS += passes/cmds/select.o OBJS += passes/cmds/show.o OBJS += passes/cmds/stat.o OBJS += passes/cmds/cover.o +OBJS += passes/cmds/design.o include passes/proc/Makefile.inc include passes/opt/Makefile.inc @@ -159,6 +160,8 @@ include passes/abc/Makefile.inc include backends/verilog/Makefile.inc include backends/ilang/Makefile.inc +include techlibs/common/Makefile.inc + endif top-all: $(TARGETS) $(EXTRA_TARGETS) |