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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:29:42 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:29:42 +0200 |
| commit | 674f421b476295d3376ec00644181fc9be02ccaf (patch) | |
| tree | 227c0083c43d9f9f5d3b671404da5c8724cea737 | |
| parent | b64b38eea2e9a7de30d6045f069c86bf4446134f (diff) | |
| download | yosys-674f421b476295d3376ec00644181fc9be02ccaf.tar.gz yosys-674f421b476295d3376ec00644181fc9be02ccaf.tar.bz2 yosys-674f421b476295d3376ec00644181fc9be02ccaf.zip | |
Bugfix in iopadmap
| -rw-r--r-- | passes/techmap/iopadmap.cc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc index 194e06a4a..9cd23ce6f 100644 --- a/passes/techmap/iopadmap.cc +++ b/passes/techmap/iopadmap.cc @@ -164,8 +164,10 @@ struct IopadmapPass : public Pass { log("Mapping port %s.%s using %s.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire->name), celltype.c_str()); RTLIL::Wire *new_wire = NULL; - if (!portname2.empty()) + if (!portname2.empty()) { new_wire = module->addWire(NEW_ID, wire); + module->swap_names(new_wire, wire); + } if (flag_bits) { |