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* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-083-28/+51
* Bump versiongithub-actions[bot]2021-08-071-1/+1
* verilog: Support tri/triand/trior wire types.Marcelina Kościelnicka2021-08-061-0/+3
* Bump versiongithub-actions[bot]2021-08-051-1/+1
* memory_share: Don't skip ports with EN wired to input for SAT sharing.Marcelina Kościelnicka2021-08-041-3/+1
* Bump versiongithub-actions[bot]2021-08-041-1/+1
* memory_bram: Move init data swizzling before other swizzling.Marcelina Kościelnicka2021-08-031-18/+18
* Bump versiongithub-actions[bot]2021-08-031-1/+1
* Require latest verificMiodrag Milanovic2021-08-021-1/+1
* Bump versiongithub-actions[bot]2021-08-021-1/+1
* backend/verilog: Add alternate mode for transparent read port output.Marcelina Kościelnicka2021-08-011-1/+71
* memory_bram: Some refactoringMarcelina Kościelnicka2021-08-011-196/+174
* Bump versiongithub-actions[bot]2021-07-311-1/+1
* Update version.ymlMiodrag Milanović2021-07-301-2/+5
* Fixes xc7 BRAM36sMaciej Dudek2021-07-301-4/+6
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-294-2/+386
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-292-0/+26
* Bump versiongithub-actions[bot]2021-07-301-1/+1
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-293-24/+55
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-284-4/+54
* Bump versiongithub-actions[bot]2021-07-291-1/+1
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-285-55/+87
* backends/verilog: Support meminit with mask.Marcelina Kościelnicka2021-07-281-3/+18
* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-2810-13/+86
* Bump versiongithub-actions[bot]2021-07-281-1/+1
* proc: Run opt_expr at the endMarcelina Kościelnicka2021-07-271-0/+11
* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-273-3/+37
* Bump versiongithub-actions[bot]2021-07-271-1/+1
* Add version bump workflowMiodrag Milanovic2021-07-261-0/+31
* Update to latest verificMiodrag Milanovic2021-07-211-3/+3
* Use new read_id_num helper function elsewhere in hierarchy.ccRupert Swarbrick2021-07-201-5/+6
* Extract connection checking logic from expand_module in hierarchy.ccRupert Swarbrick2021-07-201-23/+64
* Merge pull request #2885 from whitequark/cxxrtl-fix-2883whitequark2021-07-201-2/+8
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| * cxxrtl: treat wires with multiple defs as not inlinable.whitequark2021-07-201-2/+8
* | Merge pull request #2884 from whitequark/cxxrtl-fix-2882whitequark2021-07-201-10/+12
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| * cxxrtl: treat assignable internal wires used only for debug as locals.whitequark2021-07-201-10/+12
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* Merge pull request #2881 from whitequark/cxxrtl-sideways-colonwhitequark2021-07-201-1/+14
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| * cxxrtl: escape colon in variable names in VCD writer.whitequark2021-07-191-1/+14
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* Merge pull request #2880 from whitequark/cxxrtl-fix-2877whitequark2021-07-181-0/+16
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| * cxxrtl: add debug_item::{get,set}.whitequark2021-07-181-0/+16
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* Merge pull request #2879 from whitequark/cxxrtl-fix-2739-againwhitequark2021-07-171-0/+6
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| * cxxrtl: treat internal wires used only for debug as constants.whitequark2021-07-171-0/+6
* | Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-1619-4/+247
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* Merge pull request #2874 from whitequark/cxxrtl-fix-2589whitequark2021-07-161-9/+6
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| * cxxrtl: run hierarchy pass regardless of (*top*) attribute presence.whitequark2021-07-161-9/+6
* | Merge pull request #2873 from whitequark/cxxrtl-fix-2500whitequark2021-07-161-3/+3
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| * | cxxrtl: emit debug items for unused public wires.whitequark2021-07-161-3/+3
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* | Merge pull request #2872 from whitequark/cxxrtl-fix-2521whitequark2021-07-161-2/+2
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| * cxxrtl: don't expect user cell inputs to be wires.whitequark2021-07-161-2/+2
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* Merge pull request #2871 from whitequark/cxxrtl-fix-2540-2841whitequark2021-07-161-1/+1
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