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* | | | | | | Add missing <deque> include (MSVC build fix)Clifford Wolf2018-07-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Upodate ABC to git rev ae6716bClifford Wolf2018-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Add missing -lz to MXE buildClifford Wolf2018-07-221-1/+1
| |_|_|/ / / |/| | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #586 from hzeller/more-sourcepos-loggingClifford Wolf2018-07-204-137/+131
|\ \ \ \ \ \ | | | | | | | | | | | | | | Convert more log_error() to log_file_error() where possible.
| * | | | | | Convert more log_error() to log_file_error() where possible.Henner Zeller2018-07-204-137/+131
|/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | Mostly statements that span over multiple lines and haven't been caught with the previous conversion.
* | | | | | Merge pull request #585 from hzeller/use-file-warning-errorClifford Wolf2018-07-203-82/+79
|\ \ \ \ \ \ | | | | | | | | | | | | | | Use log_file_warning(), log_file_error() functions
| * | | | | | Use log_file_warning(), log_file_error() functions.Henner Zeller2018-07-203-82/+79
|/ / / / / / | | | | | | | | | | | | | | | | | | Wherever we can report a source-level location.
* | | | | | Merge pull request #584 from hzeller/provide-source-location-loggingClifford Wolf2018-07-203-47/+47
|\ \ \ \ \ \ | | | | | | | | | | | | | | Provide source-location logging.
| * | | | | | Provide source-location logging.Henner Zeller2018-07-193-47/+47
|/ / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | o Provide log_file_warning() and log_file_error() that prefix the log message with <filename>:<lineno>: to be easily picked up by IDEs that need to step through errors. o Simplify some duplicate logging code in kernel/log.cc o Use the new log functions in genrtlil.
* | | | | | Add async2sync passClifford Wolf2018-07-192-0/+148
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | | | * Merge pull request #2 from YosysHQ/masterAman Goel2018-07-1813-9/+1242
| | | | | |\ | |_|_|_|_|/ |/| | | | | Merging with official repo
* | | | | | Fix handling of eventually properties in verific importerClifford Wolf2018-07-171-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Fix verific -vlog-incdir and -vlog-libdir handlingClifford Wolf2018-07-161-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Merge pull request #581 from daveshah1/ecp5Clifford Wolf2018-07-1610-3/+1200
|\ \ \ \ \ \ | | | | | | | | | | | | | | Adding ECP5 synthesis target
| * | | | | | ecp5: Fixing miscellaneous sim model issuesDavid Shah2018-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Fixing 'X' issues with LUT simulation modelsDavid Shah2018-07-161-6/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: ECP5 synthesis fixesDavid Shah2018-07-163-15/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Adding synchronous set/reset supportDavid Shah2018-07-145-24/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Add DRAM match ruleDavid Shah2018-07-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Cells and mappings fixesDavid Shah2018-07-132-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Fixing arith_mapDavid Shah2018-07-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Initial arith_map implementationDavid Shah2018-07-133-6/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Adding basic synth_ecp5 based on synth_ice40David Shah2018-07-133-7/+345
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Adding DFF mapsDavid Shah2018-07-132-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Adding DRAM mapDavid Shah2018-07-133-1/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | | | | | ecp5: Adding basic cells_sim and mapper for LUTs up to LUT7David Shah2018-07-132-0/+473
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | | | | | | Fix "read -incdir"Clifford Wolf2018-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-07-161-2/+6
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| * | | | | | | Merge pull request #580 from daveshah1/ice40_nxClifford Wolf2018-07-131-2/+6
| |\| | | | | | | | |_|_|/ / / | |/| | | | | ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC
| | * | | | | ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LCDavid Shah2018-07-131-2/+6
| |/ / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* / / / / / Add "read -incdir"Clifford Wolf2018-07-161-0/+19
|/ / / / / | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | | | * Merge branch 'YosysHQ-master'Aman Goel2018-07-0428-189/+1348
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| | | | | * Merging with official repoAman Goel2018-07-0428-189/+1348
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* | | | | Fix verific eventually handlingClifford Wolf2018-06-291-6/+5
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add verific support for eventually propertiesClifford Wolf2018-06-291-5/+105
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add "verific -formal" and "read -formal"Clifford Wolf2018-06-291-7/+15
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add "read -sv -D" supportClifford Wolf2018-06-281-2/+25
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Add "read -undef"Clifford Wolf2018-06-281-0/+32
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Fix handling of signed memoriesClifford Wolf2018-06-281-0/+3
| |_|/ / |/| | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Add YOSYS_NOVERIFIC env variable for temporarily disabling verificClifford Wolf2018-06-221-22/+40
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Add simplified "read" command, enable extnets in implicit Verific importClifford Wolf2018-06-211-0/+84
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge branch 'master' of github.com:YosysHQ/yosysClifford Wolf2018-06-201-1/+1
|\ \ \ \
| * \ \ \ Merge pull request #572 from q3k/q3k/fix-protobuf-buildClifford Wolf2018-06-201-1/+1
| |\ \ \ \ | | | | | | | | | | | | Fix protobuf build
| | * | | | Fix protobuf buildSergiusz Bazanski2018-06-201-1/+1
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* / / / / Add automatic verific import in hierarchy commandClifford Wolf2018-06-203-1/+75
|/ / / / | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #571 from q3k/q3k/protobuf-backendClifford Wolf2018-06-195-0/+560
|\ \ \ \ | | | | | | | | | | Add Protobuf backend
| * | | | Add Protobuf backendSerge Bazanski2018-06-195-0/+560
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Serge Bazanski <q3k@symbioticeda.com>
* | | | | Be slightly less aggressive in "deminout" passClifford Wolf2018-06-191-4/+28
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #570 from edcote/patch-4Clifford Wolf2018-06-191-4/+4
|\ \ \ \ \ | |/ / / / |/| | | | Include module name for area summary stats
| * | | | Include module name for area summary statsEdmond Cote2018-06-181-4/+4
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PR prints the name of the module when displaying the final area count. Pros: - Easier for the user to `grep` for area information about a specific module Cons: - Arguably more verbose, less "pretty" than author desires Verification: ~~~~ 30c30 < Chip area for this module: 20616.349000 --- > Chip area for module '$paramod$d1738fc0bb353d517bc2caf8fef2abb20bced034\picorv32': 20616.349000 70c70 < Chip area for this module: 88.697700 --- > Chip area for module '\picorv32_axi_adapter': 88.697700 102c102 < Chip area for this module: 20705.046700 --- > Chip area for top module '\picorv32_axi': 20705.046700 ~~~~
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