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Age
Files
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*
Update doc
Eddie Hung
2019-08-23
1
-12
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+19
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Remove (* init *) entry when consumed into SRL
Eddie Hung
2019-08-23
1
-2
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+6
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indo -> into
Eddie Hung
2019-08-23
1
-1
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+1
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Forgot to slice
Eddie Hung
2019-08-23
1
-1
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+2
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Cope with possibility that D could connect to Q on same cell
Eddie Hung
2019-08-23
1
-1
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+1
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Mention shregmap -tech xilinx is superseded
Eddie Hung
2019-08-23
1
-1
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+1
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xilinx_srl now copes with word-level flops $dff{,e}
Eddie Hung
2019-08-23
1
-8
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+3
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xilinx_srl to use 'slice' features of pmgen for word level
Eddie Hung
2019-08-23
2
-32
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+49
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Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl
Eddie Hung
2019-08-23
5
-34
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+280
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Fix port hanlding in pmgen
Clifford Wolf
2019-08-23
1
-4
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+3
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Add pmgen slices and choices
Clifford Wolf
2019-08-23
5
-28
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+277
*
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Eddie Hung
2019-08-23
9
-20
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+43
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Forgot one
Eddie Hung
2019-08-23
1
-1
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+2
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Put abc_* attributes above port
Eddie Hung
2019-08-23
3
-14
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+28
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Merge pull request #1326 from mmicko/doc-update
Eddie Hung
2019-08-23
1
-2
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+5
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Make macOS depenency clear
Miodrag Milanovic
2019-08-23
1
-2
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+5
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Do not propagate mem2reg attribute through to result
Eddie Hung
2019-08-22
2
-1
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+3
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Spelling
Eddie Hung
2019-08-22
1
-2
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+2
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Merge pull request #1322 from mmicko/pyosys_osx
Eddie Hung
2019-08-22
1
-0
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+2
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do not require boost if pyosys is not used
Miodrag Milanovic
2019-08-22
1
-0
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+2
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Merge pull request #1319 from TeaEngineering/shuckc/brew-tcl-tk
Eddie Hung
2019-08-22
1
-0
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+1
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require tcl-tk in Brewfile
Chris Shucksmith
2019-08-22
1
-0
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+1
*
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In sat: 'x' in init attr should not override constant
Eddie Hung
2019-08-22
3
-1
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+7
*
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Remove Xilinx test
Eddie Hung
2019-08-22
1
-34
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+0
*
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Actually, there might not be any harm in updating sigmap...
Eddie Hung
2019-08-22
1
-3
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+1
*
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Add comment as per @cliffordwolf
Eddie Hung
2019-08-22
1
-0
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+11
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Add shregmap -tech xilinx test
Eddie Hung
2019-08-22
1
-0
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+1
*
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Revert "Try way that doesn't involve creating a new wire"
Eddie Hung
2019-08-22
1
-15
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+10
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Try way that doesn't involve creating a new wire
Eddie Hung
2019-08-22
1
-10
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+15
*
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If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung
2019-08-22
1
-3
/
+6
*
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Add doc
Eddie Hung
2019-08-22
1
-1
/
+14
*
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Add copyright
Eddie Hung
2019-08-22
1
-0
/
+1
*
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Add CHANGELOG entry
Eddie Hung
2019-08-22
1
-0
/
+2
*
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Remove `shregmap -tech xilinx` additions
Eddie Hung
2019-08-22
1
-189
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+8
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pmgen to also iterate over all module ports
Eddie Hung
2019-08-22
1
-2
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+4
*
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Remove output_bits
Eddie Hung
2019-08-22
2
-16
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+7
*
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Forgot to set ud_variable.minlen
Eddie Hung
2019-08-22
1
-0
/
+1
*
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Do not run xilinx_srl_pm in fixed loop
Eddie Hung
2019-08-22
1
-28
/
+24
*
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Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl
Eddie Hung
2019-08-22
19
-102
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+1046
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Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx
Eddie Hung
2019-08-22
2
-4
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+96
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Copy-paste typo
Eddie Hung
2019-08-22
1
-1
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+1
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Respect opt_expr -keepdc as per @cliffordwolf
Eddie Hung
2019-08-22
2
-1
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+15
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Handle $shift and Y_WIDTH > 1 as per @cliffordwolf
Eddie Hung
2019-08-22
2
-5
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+51
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Add cover()
Eddie Hung
2019-08-22
1
-0
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+1
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Canonical form
Eddie Hung
2019-08-22
1
-5
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+5
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Add test
Eddie Hung
2019-08-21
1
-0
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+14
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opt_expr to trim A port of $shiftx if Y_WIDTH == 1
Eddie Hung
2019-08-21
1
-0
/
+17
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*
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Bump year in copyright notice
Clifford Wolf
2019-08-22
3
-3
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+3
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*
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Fix missing newline at end of file
Clifford Wolf
2019-08-22
1
-1
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+1
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*
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Merge pull request #1289 from mmicko/anlogic_fixes
Clifford Wolf
2019-08-22
5
-91
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+162
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