| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | Added "write_smv" skeleton | Clifford Wolf | 2015-06-15 | 3 | -2/+265 | |
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| * | Removed debug code from write_smt2 | Clifford Wolf | 2015-06-14 | 1 | -2/+0 | |
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| * | Modernized memory_dff (and fixed a bug) | Clifford Wolf | 2015-06-14 | 2 | -151/+166 | |
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| * | Added "memory -nordff" | Clifford Wolf | 2015-06-14 | 1 | -2/+9 | |
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| * | Added write_smt2 -mem | Clifford Wolf | 2015-06-14 | 1 | -80/+157 | |
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| * | Makefile fix for YosysJS build | Clifford Wolf | 2015-06-11 | 1 | -0/+4 | |
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| * | Fixed cstr_buf for std::string with small string optimization | Clifford Wolf | 2015-06-11 | 6 | -5/+16 | |
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| * | Improvements in cellaigs.cc and "json -aig" | Clifford Wolf | 2015-06-11 | 2 | -10/+215 | |
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| * | AigMaker refactoring | Clifford Wolf | 2015-06-10 | 4 | -78/+153 | |
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| * | Added "json -aig" | Clifford Wolf | 2015-06-10 | 3 | -9/+76 | |
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| * | Renamed "aig" to "aigmap" | Clifford Wolf | 2015-06-10 | 3 | -10/+10 | |
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| * | Fixed cellaigs port extending | Clifford Wolf | 2015-06-10 | 3 | -3/+11 | |
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| * | Added "aig" pass | Clifford Wolf | 2015-06-09 | 3 | -16/+291 | |
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| * | synth_ice40 now flattens by default | Clifford Wolf | 2015-06-09 | 1 | -4/+8 | |
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| * | Added cellaigs API | Clifford Wolf | 2015-06-09 | 4 | -2/+173 | |
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| * | Merge clock inverters in memory_dff | Clifford Wolf | 2015-06-09 | 1 | -16/+37 | |
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| * | Merge branch 'verilog-backend-memV2' of github.com:wluker/yosys | Clifford Wolf | 2015-06-09 | 1 | -54/+110 | |
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| | * | $mem cell in verilog backend : grouped writes by clock | luke whittlesey | 2015-06-08 | 2 | -58/+110 | |
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| | * | Bug fix in $mem verilog backend + changed tests/bram flow of make test. | luke whittlesey | 2015-06-04 | 2 | -16/+20 | |
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| * | | Fixed "avail_parameters" handling in module clone/copy | Clifford Wolf | 2015-06-08 | 1 | -0/+2 | |
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| * | | Added log_dump() support for IdStrings | Clifford Wolf | 2015-06-08 | 2 | -0/+5 | |
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| * | | Fixed handling of parameters with reversed range | Clifford Wolf | 2015-06-08 | 1 | -1/+1 | |
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| * | Added opt_share -share_all | Clifford Wolf | 2015-05-31 | 2 | -16/+32 | |
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| * | Added iCE40 PLL cells | Clifford Wolf | 2015-05-31 | 1 | -0/+168 | |
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| * | Added liberty dont_use support to dfflibmap | Clifford Wolf | 2015-05-31 | 1 | -0/+4 | |
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| * | Fixed signedness of genvar expressions | Clifford Wolf | 2015-05-29 | 1 | -2/+2 | |
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| * | Added output args to synth_ice40 | Clifford Wolf | 2015-05-26 | 2 | -2/+37 | |
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| * | Improvements in BLIF front-end | Clifford Wolf | 2015-05-24 | 2 | -4/+51 | |
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| * | improved ice40 SB_IO sim model | Clifford Wolf | 2015-05-23 | 1 | -16/+9 | |
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| * | Improved "flatten" handlings of inout ports | Clifford Wolf | 2015-05-23 | 1 | -2/+26 | |
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| * | Added simple $dlatch support to opt_rmdff | Clifford Wolf | 2015-05-23 | 1 | -0/+35 | |
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| * | Added ice40 SB_IO sim model | Clifford Wolf | 2015-05-23 | 1 | -1/+46 | |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2015-05-22 | 1 | -19/+23 | |
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| | * | Some fixes for $mem in verilog back-end | Clifford Wolf | 2015-05-20 | 1 | -19/+23 | |
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| * | | preserve used $-wires with init attribute in opt_clean | Clifford Wolf | 2015-05-22 | 1 | -1/+1 | |
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| * | bugfix in blif front-end | Clifford Wolf | 2015-05-18 | 2 | -6/+6 | |
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| * | added vloghtb test_febe.sh | Clifford Wolf | 2015-05-17 | 2 | -0/+49 | |
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| * | Improved .latch support in BLIF front-end | Clifford Wolf | 2015-05-17 | 1 | -3/+30 | |
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| * | Added read_blif command | Clifford Wolf | 2015-05-17 | 2 | -1/+33 | |
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| * | Generalized blifparse API | Clifford Wolf | 2015-05-17 | 3 | -21/+31 | |
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| * | abc/blifparse files reorganization | Clifford Wolf | 2015-05-17 | 7 | -8/+9 | |
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| * | Verific build fixes | Clifford Wolf | 2015-05-17 | 5 | -7/+7 | |
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| * | Added .barbuf support to abc BLIF parser | Clifford Wolf | 2015-05-13 | 1 | -0/+20 | |
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| * | changed file() to open() in python scripts | Clifford Wolf | 2015-05-11 | 4 | -11/+11 | |
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| * | Merge pull request #63 from wluker/verilog-backend-mem | Clifford Wolf | 2015-05-11 | 1 | -1/+2 | |
| |\ | | | | | Fixed bug in $mem cell verilog code generation. | |||||
| | * | Fixed bug in $mem cell verilog code generation. | luke whittlesey | 2015-05-11 | 1 | -11/+12 | |
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| * | | Disabled broken $mem support in verilog backend | Clifford Wolf | 2015-05-10 | 1 | -11/+11 | |
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| * | Merge pull request #62 from wluker/verilog-backend-mem | Clifford Wolf | 2015-05-10 | 1 | -1/+164 | |
| |\ | | | | | Added support for $mem cells in the verilog backend. | |||||
| | * | Made changes recommended by Clifford Wolf ... | luke whittlesey | 2015-05-10 | 1 | -22/+11 | |
| | | | | | | | | | | | | | Removed bit_check_equal(), used RTLIL::SigBit for individual bits, used dict<> instead of std::map, and used RTLIL::SigSpec instead of std::vector. | |||||
| | * | Verilog backend for $mem cells should now be able to handle different | luke whittlesey | 2015-05-08 | 1 | -50/+105 | |
| | | | | | | | | | write-enable bits and RD_TRANSPARENT parameter settings. | |||||
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