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| | * | Add "read_verilog -pwires" feature, closes #1106Clifford Wolf2019-06-196-9/+48
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-195-16/+92
| |\ \ | | | | | | | | Improve handling of initial/default values
| | * | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Use input default values in hierarchy passClifford Wolf2019-06-191-0/+38
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Add defaultvalue attributeClifford Wolf2019-06-192-0/+15
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * | Fix handling of "logic" variables with initial valueClifford Wolf2019-06-191-2/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | | Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-195-0/+8
| |\ \ | | | | | | | | Support ~ in filename parsing
| | * | Support filename rewrite in backendsBen Widawsky2019-06-184-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| | * | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on Linux only v2: Wrap functioanlity in ifndef _WIN32 (eddiehung) Find '~/' instead of '~' (cliffordwolf) Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | Merge pull request #1104 from whitequark/case-semanticsClifford Wolf2019-06-192-1/+40
| |\ \ \ | | |/ / | |/| | Clarify switch/case semantics in RTLIL
| | * | Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
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| | * | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* | | Merge branch 'xaig' into xc7muxEddie Hung2019-06-194-21/+9
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| * | | Remove iterator based Module::remove as per @cliffordwolfEddie Hung2019-06-183-18/+9
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| * | | Remove unncessary headerEddie Hung2019-06-181-3/+0
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| * | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-183-3/+15
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* | | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-183-3/+15
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| * | | Merge pull request #1086 from udif/pr_elab_sys_tasks2Clifford Wolf2019-06-182-3/+13
| |\ \ \ | | |_|/ | |/| | Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)
| | * | Fixed brojen $error()/$info/$warning() on non-generate blocksUdi Finkelstein2019-06-112-3/+13
| | | | | | | | | | | | | | | | (within always/initial blocks)
| * | | Add timescale and generated-by header to yosys-smtbmc MkVcdClifford Wolf2019-06-161-0/+2
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-181-29/+27
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| * | | Really permute Xilinx LUT mappings as default LUT6.I5:A6Eddie Hung2019-06-181-16/+16
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| * | | Revert "Fix (do not) permute LUT inputs, but permute mux selects"Eddie Hung2019-06-181-33/+31
| | | | | | | | | | | | | | | | This reverts commit da3d2eedd2b6391621e81b3eaaa28a571e058f9d.
* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-182-37/+37
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| * | | Clean upEddie Hung2019-06-181-6/+4
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| * | | Fix (do not) permute LUT inputs, but permute mux selectsEddie Hung2019-06-181-31/+33
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-9/+8
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| * | | Fix copy-pasta issueEddie Hung2019-06-171-9/+8
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-172-33/+59
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| * | | Permute INIT for +/xilinx/lut_map.vEddie Hung2019-06-171-32/+58
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| * | | Simplify commentEddie Hung2019-06-171-1/+1
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-5/+5
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| * | | Update LUT7/8 delays to take account for [ABC]OUTMUX delayEddie Hung2019-06-171-5/+5
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-1/+1
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| * | | &scorr before &sweep, remove &retime as recommendedEddie Hung2019-06-171-1/+1
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-3/+4
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| * | | Copy not move parameters/attributesEddie Hung2019-06-171-3/+4
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-173-27/+37
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| * | | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-173-27/+37
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-171-1/+1
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| * | | Try -W 300Eddie Hung2019-06-171-1/+2
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| * | | Re-enable &dc2Eddie Hung2019-06-171-1/+1
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* | | | Try -W 300Eddie Hung2019-06-161-1/+2
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-163-299/+33
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| * | | CleanupEddie Hung2019-06-163-299/+33
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-151-2/+2
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| * | | Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> OEddie Hung2019-06-151-2/+2
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* | | | Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-141-1/+3
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| * | | Leave breadcrumb behindEddie Hung2019-06-141-0/+2
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