| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added "write_verilog -nodec -nostr" | Clifford Wolf | 2016-07-30 | 1 | -4/+27 |
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| * | Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() | Clifford Wolf | 2016-07-25 | 3 | -3/+3 |
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| * | Fixed a verilog parser memory leak | Clifford Wolf | 2016-07-25 | 1 | -0/+1 |
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| * | Fixed parsing of empty positional cell ports | Clifford Wolf | 2016-07-25 | 1 | -2/+31 |
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| * | Improvements in CellEdgesDatabase | Clifford Wolf | 2016-07-24 | 3 | -16/+167 |
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| * | Added CellEdgesDatabase API | Clifford Wolf | 2016-07-24 | 4 | -1/+250 |
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| * | Moved SatHelper::setup_init() code to SatHelper::setup() | Clifford Wolf | 2016-07-24 | 1 | -97/+92 |
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| * | Added $initstate support to "sat" command | Clifford Wolf | 2016-07-23 | 1 | -13/+12 |
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| * | No tristate warning message for "read_verilog -lib" | Clifford Wolf | 2016-07-23 | 3 | -8/+11 |
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| * | Added satgen initstate support | Clifford Wolf | 2016-07-22 | 1 | -0/+27 |
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| * | Using $initstate in "initial assume" and "initial assert" | Clifford Wolf | 2016-07-21 | 1 | -1/+6 |
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| * | Added $initstate cell type and vlog function | Clifford Wolf | 2016-07-21 | 7 | -4/+54 |
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| * | After reading the SV spec, using non-standard predict() instead of expect() | Clifford Wolf | 2016-07-21 | 16 | -32/+28 |
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| * | Added basic support for $expect cells | Clifford Wolf | 2016-07-13 | 16 | -19/+82 |
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| * | Added examples/smtbmc | Clifford Wolf | 2016-07-13 | 2 | -0/+30 |
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| * | Merge pull request #191 from whitequark/json-module-attributes | Clifford Wolf | 2016-07-13 | 1 | -2/+6 |
| |\ | | | | | write_json: also write module attributes | ||||
| | * | write_json: also write module attributes. | whitequark | 2016-07-12 | 1 | -2/+6 |
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| * | | Merge pull request #193 from azonenberg/master | Clifford Wolf | 2016-07-13 | 2 | -2/+9 |
| |\ \ | | | | | | | Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP | ||||
| | * \ | Merge https://github.com/cliffordwolf/yosys | Andrew Zonenberg | 2016-07-12 | 1 | -2/+5 |
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| * | | | Minor bugfix in FSM reset state detection | Clifford Wolf | 2016-07-12 | 1 | -2/+5 |
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| | * | Added GP_DAC cell | Andrew Zonenberg | 2016-07-11 | 1 | -0/+8 |
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| | * | Removed VOUT port of GP_BANDGAP | Andrew Zonenberg | 2016-07-11 | 1 | -1/+1 |
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| | * | Removed splitnets in prep for new gp4par parser | Andrew Zonenberg | 2016-07-11 | 1 | -1/+0 |
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| * | Yosys-smtbmc: Support for hierarchical VCD dumping | Clifford Wolf | 2016-07-11 | 2 | -23/+59 |
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| * | Moved smt2 yosys info parsing from smtbmc.py to smtio.py | Clifford Wolf | 2016-07-11 | 3 | -16/+56 |
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| * | Added "prep -auto-top" and "synth -auto-top" | Clifford Wolf | 2016-07-11 | 2 | -6/+23 |
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| * | Merge branch 'master' of github.com:cliffordwolf/yosys | Clifford Wolf | 2016-07-10 | 1 | -0/+26 |
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| | * | Merge pull request #189 from whitequark/master | Clifford Wolf | 2016-07-10 | 1 | -0/+26 |
| | |\ | | | | | | | greenpak4: add GP_COUNT{8,14}_ADV cells | ||||
| | | * | greenpak4: add GP_COUNT{8,14}_ADV cells. | whitequark | 2016-07-10 | 1 | -0/+26 |
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| * / | Support for hierarchical designs in smt2 back-end | Clifford Wolf | 2016-07-10 | 2 | -24/+144 |
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| * | Further improved fsm_detect output, attempt to detect self-resetting circuits | Clifford Wolf | 2016-07-09 | 1 | -6/+68 |
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| * | Added printing of some warning messages to fsm_detect | Clifford Wolf | 2016-07-09 | 1 | -14/+61 |
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| * | Added warning about adding fsm_encoding attributes to wires to manual | Clifford Wolf | 2016-07-08 | 1 | -0/+4 |
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| * | Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations | Clifford Wolf | 2016-07-08 | 2 | -13/+24 |
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| * | Fixed mem assignment in left-hand-side concatenation | Clifford Wolf | 2016-07-08 | 2 | -0/+57 |
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| * | Merge branch 'eddiehung-vtr' | Clifford Wolf | 2016-07-08 | 1 | -9/+17 |
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| | * | Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior | Clifford Wolf | 2016-07-08 | 1 | -13/+15 |
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| | * | In BLIF, a .names without entries already always outputs 0 | Clifford Wolf | 2016-07-08 | 1 | -11/+0 |
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| | * | Undo eddiehung-vtr Makefile changes | Clifford Wolf | 2016-07-08 | 1 | -5/+1 |
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| | * | Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into ↵ | Clifford Wolf | 2016-07-08 | 2 | -3/+24 |
| |/| | | | | | | | eddiehung-vtr | ||||
| | * | Fix for all zero mask | eddiehung | 2015-05-03 | 2 | -1/+16 |
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| | * | Escape '<' and '>' some more | eddiehung | 2015-05-03 | 1 | -1/+1 |
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| | * | For vtr, escape angle brackets as well | eddiehung | 2015-04-28 | 1 | -1/+1 |
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| | * | blifwriter: write out .names for true/false/undef type == '-' | eddiehung | 2015-04-28 | 1 | -0/+6 |
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| * | | Fixed autotest.sh handling of `timescale | Clifford Wolf | 2016-07-02 | 1 | -14/+10 |
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| * | | Merge branch 'assert-limit' | Clifford Wolf | 2016-07-01 | 1 | -9/+33 |
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| | * | | Replaced "select -assert-limit" with -assert-max and -assert-min | Clifford Wolf | 2016-07-01 | 1 | -42/+29 |
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| | * | | Added 'assert-limit' option for 'select' command | eshellko | 2016-07-01 | 1 | -5/+42 |
| |/ / | | | | | For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done. | ||||
| * | | Improved ice40_ffinit error reporting | Clifford Wolf | 2016-06-30 | 1 | -1/+5 |
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| * | | Merge pull request #181 from rubund/input_logic_allowed | Clifford Wolf | 2016-06-21 | 1 | -2/+2 |
| |\ \ | | | | | | | Allow defining input ports as "input logic" in SystemVerilog | ||||
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index : iCE40/yosys | |
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