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authorClifford Wolf <clifford@clifford.at>2016-07-13 09:24:31 +0200
committerGitHub <noreply@github.com>2016-07-13 09:24:31 +0200
commit9e5c9471e366e1abaad62525e783eb549274d951 (patch)
treed8fb4fe351749c43892c46d20b3a75871b39692d
parente92998a79cec635270a350117eddb52c6232f388 (diff)
parent32bea97b757e11002133d8e69b23eac3df7fb800 (diff)
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Merge pull request #193 from azonenberg/master
Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP
-rw-r--r--techlibs/greenpak4/cells_sim.v10
-rw-r--r--techlibs/greenpak4/synth_greenpak4.cc1
2 files changed, 9 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 67f00f3a4..ca8556a85 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -36,7 +36,7 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT
endmodule
-module GP_BANDGAP(output reg OK, output reg VOUT);
+module GP_BANDGAP(output reg OK);
parameter AUTO_PWRDN = 1;
parameter CHOPPER_EN = 1;
parameter OUT_DELAY = 100;
@@ -120,6 +120,14 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
endmodule
+module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
+
+ initial VOUT = 0;
+
+ //analog hard IP is not supported for simulation
+
+endmodule
+
module GP_DELAY(input IN, output reg OUT);
parameter DELAY_STEPS = 1;
diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc
index 50820a600..c8f81a18d 100644
--- a/techlibs/greenpak4/synth_greenpak4.cc
+++ b/techlibs/greenpak4/synth_greenpak4.cc
@@ -195,7 +195,6 @@ struct SynthGreenPAK4Pass : public ScriptPass
if (check_label("json"))
{
- run("splitnets;;", "(temporary workaround for gp4par parser limitation)");
if (!json_file.empty() || help_mode)
run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
}