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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-07-12 16:12:37 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-07-12 16:12:37 -0700 |
| commit | 32bea97b757e11002133d8e69b23eac3df7fb800 (patch) | |
| tree | d8fb4fe351749c43892c46d20b3a75871b39692d | |
| parent | 52a738a54435d9e54ac7cb523551ae866cc76770 (diff) | |
| parent | e92998a79cec635270a350117eddb52c6232f388 (diff) | |
| download | yosys-32bea97b757e11002133d8e69b23eac3df7fb800.tar.gz yosys-32bea97b757e11002133d8e69b23eac3df7fb800.tar.bz2 yosys-32bea97b757e11002133d8e69b23eac3df7fb800.zip | |
Merge https://github.com/cliffordwolf/yosys
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 95cb498e3..8a4ee3f26 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -92,12 +92,15 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef()) do { + SigSpec new_reset_state; if (sig_aa.is_fully_def()) - *reset_state = sig_aa.as_const(); + new_reset_state = sig_aa.as_const(); else if (sig_bb.is_fully_def()) - *reset_state = sig_bb.as_const(); + new_reset_state = sig_bb.as_const(); else break; + new_reset_state.extend_u0(GetSize(*reset_state)); + *reset_state = new_reset_state.as_const(); log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state)); } while (0); |