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* Bump versionClifford Wolf2019-09-301-1/+1
* Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2syncClifford Wolf2019-09-301-0/+2
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| * equiv_opt to call async2sync when not -multiclock like SymbiYosysEddie Hung2019-09-271-0/+2
* | Merge pull request #1417 from YosysHQ/clifford/fixasync2syncClifford Wolf2019-09-301-0/+1
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| * | Fix $dlatch handling in async2syncClifford Wolf2019-09-301-0/+1
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* | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
* | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
* | synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-303-2/+77
* | Merge pull request #1414 from hzeller/improve-replace-with-empty-mapEddie Hung2019-09-291-0/+2
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| * | Avoid work in replace() if rules empty.Henner Zeller2019-09-291-0/+2
* | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2944-281/+6234
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| * | | Re-orderEddie Hung2019-09-272-2/+2
| * | | Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
| * | | Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
| * | | Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
| * | | Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-262-7/+3
| * | | Update docEddie Hung2019-09-261-1/+2
| * | | Zero out portsEddie Hung2019-09-261-2/+2
| * | | xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-262-454/+172
| * | | Try recursive pmgen for P cascadeEddie Hung2019-09-261-88/+118
| * | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
| * | | TypoEddie Hung2019-09-261-1/+1
| * | | CREG to check for \keepEddie Hung2019-09-261-0/+3
| * | | Remove newlineEddie Hung2019-09-261-1/+0
| * | | select onceEddie Hung2019-09-262-8/+12
| * | | Stop trying to be too smart by prematurely optimisingEddie Hung2019-09-263-38/+14
| * | | mul2dsp.v slice namesEddie Hung2019-09-251-5/+5
| * | | Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)Eddie Hung2019-09-251-1/+5
| * | | Reject if (* init *) presentEddie Hung2019-09-252-0/+6
| * | | Remove unnecessary check for A_SIGNED != B_SIGNED; be more explicitEddie Hung2019-09-251-3/+1
| * | | Revert "Remove _TECHMAP_CELLTYPE_ check since all $mul"Eddie Hung2019-09-251-2/+6
| * | | Revert "No need for $__mul anymore?"Eddie Hung2019-09-251-8/+8
| * | | Rework xilinx_dsp postAdd for new wreduce callEddie Hung2019-09-251-3/+3
| * | | Only wreduce on t:$addEddie Hung2019-09-251-1/+1
| * | | Remove _TECHMAP_CELLTYPE_ check since all $mulEddie Hung2019-09-251-6/+2
| * | | Fix memory issue since SigSpec& could be invalidatedEddie Hung2019-09-251-6/+10
| * | | No need for $__mul anymore?Eddie Hung2019-09-251-8/+8
| * | | unextend only used in initEddie Hung2019-09-251-2/+1
| * | | Call 'wreduce' after mul2dsp to avoid unextend()Eddie Hung2019-09-252-5/+5
| * | | Oops. Actually use __NAME__ in ABC_DSP48E1 macroEddie Hung2019-09-251-1/+1
| * | | Add (* techmap_autopurge *) to abc_unmap.v tooEddie Hung2019-09-231-11/+11
| * | | "abc_padding" attr for blackbox outputs that were padded, remove them laterEddie Hung2019-09-232-4/+22
| * | | Force $inout.out ports to begin with '$' to indicate internalEddie Hung2019-09-232-3/+3
| * | | Add techmap_autopurge to outputs in abc_map.v tooEddie Hung2019-09-231-11/+11
| * | | Revert "Add a xilinx_finalise pass"Eddie Hung2019-09-233-87/+0
| * | | Revert "Remove (* techmap_autopurge *) from abc_unmap.v since no effect"Eddie Hung2019-09-231-38/+38
| * | | Revert "Vivado does not like zero width port connections"Eddie Hung2019-09-231-2/+2
| * | | Vivado does not like zero width port connectionsEddie Hung2019-09-231-2/+2
| * | | Remove (* techmap_autopurge *) from abc_unmap.v since no effectEddie Hung2019-09-231-38/+38
| * | | Add a xilinx_finalise passEddie Hung2019-09-233-0/+87
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