iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge branch 'xaig' into xaig_dff	Eddie Hung	2019-06-17	3	-25/+37
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\| *	Fix leak removing cells during ABC integration; also preserve attr	Eddie Hung	2019-06-17	3	-27/+37
* \|	Merge remote-tracking branch 'origin/xaig' into xaig_dff	Eddie Hung	2019-06-17	2	-2/+3
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\| *	Try -W 300	Eddie Hung	2019-06-17	1	-1/+2
\| *	Re-enable &dc2	Eddie Hung	2019-06-17	1	-1/+1
* \|	Cleanup	Eddie Hung	2019-06-16	5	-73/+59
* \|	Merge branch 'xaig' into xaig_dff	Eddie Hung	2019-06-16	0	-0/+0
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\| *	Cleanup	Eddie Hung	2019-06-16	3	-299/+33
* \|	Cleanup write_xaiger	Eddie Hung	2019-06-15	1	-15/+10
* \|	Cleanup	Eddie Hung	2019-06-15	1	-40/+7
* \|	abc9 to recover_init by default	Eddie Hung	2019-06-15	1	-11/+6
* \|	Read init from outputs	Eddie Hung	2019-06-15	1	-0/+4
* \|	Add +/xilinx/abc_ff	Eddie Hung	2019-06-15	1	-0/+33
* \|	Preserve init of flops, and write into XAIG	Eddie Hung	2019-06-15	1	-5/+30
* \|	Do not treat $__ABC_FF_ as a user cell	Eddie Hung	2019-06-15	2	-30/+15
* \|	Fix spacing	Eddie Hung	2019-06-15	1	-1/+1
* \|	Update comment	Eddie Hung	2019-06-15	1	-1/+1
* \|	Cleanup	Eddie Hung	2019-06-15	1	-10/+7
* \|	Use $__ABC_FF_ instead of $_FF_	Eddie Hung	2019-06-15	3	-17/+33
* \|	Fix debug message	Eddie Hung	2019-06-15	1	-0/+1
* \|	Fix log_debug messages	Eddie Hung	2019-06-15	1	-17/+23
* \|	Re-order alphabetically	Eddie Hung	2019-06-15	1	-1/+1
* \|	Fix initialisation of flops	Eddie Hung	2019-06-15	3	-14/+15
* \|	Update comment	Eddie Hung	2019-06-15	1	-1/+1
* \|	Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues	Eddie Hung	2019-06-15	3	-15/+15
* \|	Missing close bracket	Eddie Hung	2019-06-15	1	-1/+1
* \|	Wrap FDRE with $__ABC_FDRE containing comb	Eddie Hung	2019-06-15	4	-12/+29
* \|	For now, short $_DFF_[NP]_ from ff_map.v at re-integration	Eddie Hung	2019-06-15	1	-0/+8
* \|	read_aiger to not require clk_name for latches, plus debug	Eddie Hung	2019-06-15	1	-21/+37
* \|	write_xaiger to treat abc_flop boxes as boxff for ABC	Eddie Hung	2019-06-15	1	-122/+105
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*	Fix upper XC7 LUT[78] delays to use I[01] -> O delay not S -> O	Eddie Hung	2019-06-15	1	-2/+2
*	Leave breadcrumb behind	Eddie Hung	2019-06-14	1	-0/+2
*	Remove redundant condition	Eddie Hung	2019-06-14	1	-1/+1
*	Revert "Cleanup/optimise toposort in write_xaiger"	Eddie Hung	2019-06-14	1	-44/+40
*	Update comment	Eddie Hung	2019-06-14	1	-1/+2
*	Check that whiteboxes are synthesisable	Eddie Hung	2019-06-14	1	-4/+8
*	Get rid of compiler warnings	Eddie Hung	2019-06-14	2	-7/+7
*	As per @daveshah1 remove async DFF timing from xilinx	Eddie Hung	2019-06-14	1	-2/+2
*	Cover __APPLE__ too for little to big endian	Eddie Hung	2019-06-14	2	-8/+16
*	Update abc9 -D doc	Eddie Hung	2019-06-14	1	-1/+2
*	Enable "abc9 -D <num>" for timing-driven synthesis	Eddie Hung	2019-06-14	1	-9/+9
*	Further cleanup based on @daveshah1	Eddie Hung	2019-06-14	4	-47/+47
*	Resolve comments from @daveshah1	Eddie Hung	2019-06-14	3	-17/+11
*	Add XC7_WIRE_DELAY macro to synth_xilinx.cc	Eddie Hung	2019-06-14	1	-1/+3
*	Update delays based on SymbiFlow/prjxray-db	Eddie Hung	2019-06-14	1	-12/+13
*	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	Eddie Hung	2019-06-14	4	-3/+3
*	Comment out dist RAM boxing on ECP5 for now	Eddie Hung	2019-06-14	1	-1/+1
*	Remove WIP ABC9 flop support	Eddie Hung	2019-06-14	5	-79/+79
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-14	2	-0/+46
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\| *	Merge pull request #829 from abdelrahmanhosny/master	Serge Bazanski	2019-06-13	2	-0/+46
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