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* Check latches type one by oneMiodrag Milanovic2019-10-042-40/+25
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* Removed top module where not neededMiodrag Milanovic2019-10-044-37/+4
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* Test muxes synth one by oneMiodrag Milanovic2019-10-042-38/+39
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* Cleaned verilog code from not used definesMiodrag Milanovic2019-10-041-6/+0
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* Check for MULT18X18D, since that is working nowMiodrag Milanovic2019-10-042-14/+11
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* Check flops one by oneMiodrag Milanovic2019-10-044-71/+50
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* Removed alu and div_mod tests as agreedMiodrag Milanovic2019-10-044-57/+0
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* equiv_opt with -assertEddie Hung2019-09-301-3/+1
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* Update resource count for alu.ysEddie Hung2019-09-301-3/+3
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* Move $x to end as per 7f0eec8Eddie Hung2019-09-301-1/+1
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* Update fsm.ys resource countEddie Hung2019-09-301-3/+3
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* Merge branch 'SergeyDegtyar/ecp5' of https://github.com/SergeyDegtyar/yosys ↵Eddie Hung2019-09-3037-0/+801
|\ | | | | | | into eddie/pr1352
| * Add comment to dpram test about related issue.SergeyDegtyar2019-09-181-0/+1
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| * adffs test update (equiv_opt -multiclock). div_mod test fixSergeyDegtyar2019-09-173-17/+12
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| * Remove stat command form shifter.ys testSergeyDegtyar2019-09-041-1/+1
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| * Fix ecp5 testsSergeyDegtyar2019-09-0411-2421/+26
| | | | | | | | | | - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5;
| * Uncomment sat command in memory.ys test.SergeyDegtyar2019-09-031-2/+1
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| * Add tests for ECP5 architectureSergeyDegtyar2019-09-0340-0/+3201
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* | Update doc for equiv_optEddie Hung2019-09-301-2/+3
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* | Merge pull request #1406 from whitequark/connect_rpcwhitequark2019-09-3011-0/+1767
|\ \ | | | | | | rpc: new frontend
| * | rpc: new frontend.whitequark2019-09-309-0/+744
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new pass, connect_rpc, allows any HDL frontend that can read/write JSON from/to stdin/stdout or an unix socket or a named pipe to participate in elaboration as a first class citizen, such that any other HDL supported by Yosys directly or indirectly can transparently instantiate modules handled by this frontend. Recognizing that many HDL frontends emit Verilog, it allows the RPC frontend to direct Yosys to process the result of instantiation via any built-in Yosys frontend. The resulting RTLIL is then hygienically integrated into the overall design.
| * | libs: import json11.whitequark2019-09-303-0/+1023
| | | | | | | | | | | | | | | This commit imports the code from upstream commit dropbox/json11@8ccf1f0c5ecab6151a65f216e7eeccd8588e5457.
* | | Merge pull request #1397 from btut/fix/python_wrappers_inline_constructorsEddie Hung2019-09-301-0/+2
|\ \ \ | | | | | | | | Generate Python wrappers for inline constructors
| * | | Generate Python wrappers for inline constructorsBenedikt Tutzer2019-09-231-0/+2
| | | | | | | | | | | | | | | | Fixes: #1353
* | | | Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-304-6/+10
|\ \ \ \ | | | | | | | | | | Open aig frontend as binary file
| * | | | Fix reading aig files on windowsMiodrag Milanovic2019-09-291-1/+5
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| * | | | Open aig frontend as binary fileMiodrag Milanovic2019-09-294-5/+5
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* | | | | Bump versionClifford Wolf2019-09-301-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2syncClifford Wolf2019-09-301-0/+2
|\ \ \ \ \ | | | | | | | | | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosys
| * | | | | equiv_opt to call async2sync when not -multiclock like SymbiYosysEddie Hung2019-09-271-0/+2
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* | | | | | Merge pull request #1417 from YosysHQ/clifford/fixasync2syncClifford Wolf2019-09-301-0/+1
|\ \ \ \ \ \ | | | | | | | | | | | | | | Fix $dlatch handling in async2sync
| * | | | | | Fix $dlatch handling in async2syncClifford Wolf2019-09-301-0/+1
|/ / / / / / | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | | | Add latch test modified from #1363Eddie Hung2019-09-302-0/+73
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* | | | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}Eddie Hung2019-09-306-122/+46
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* | | | | | synth_xilinx: Support latches, remove used-up FF init values.Marcin Kościelnicki2019-09-303-2/+77
| | | | | | | | | | | | | | | | | | | | | | | | Fixes #1387.
* | | | | | Merge pull request #1414 from hzeller/improve-replace-with-empty-mapEddie Hung2019-09-291-0/+2
|\ \ \ \ \ \ | | | | | | | | | | | | | | Avoid work in replace() if rules empty.
| * | | | | | Avoid work in replace() if rules empty.Henner Zeller2019-09-291-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This speeds up processing when number of bits are large but there is actually nothing to replace. Adresses part of #1382. Signed-off-by: Henner Zeller <h.zeller@acm.org>
* | | | | | | Merge pull request #1359 from YosysHQ/xc7dspEddie Hung2019-09-2944-281/+6234
|\ \ \ \ \ \ \ | |_|_|/ / / / |/| | | | | | DSP inference for Xilinx (improved for ice40, initial support for ecp5)
| * | | | | | Re-orderEddie Hung2019-09-272-2/+2
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| * | | | | | Missing (* mul2dsp *) for sliceBEddie Hung2019-09-271-2/+2
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| * | | | | | Ooops AREG and BREG to default to -1Eddie Hung2019-09-271-2/+2
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| * | | | | | Update doc with max cascade chain of 20Eddie Hung2019-09-261-2/+4
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| * | | | | | Do not always zero out C (e.g. during cascade breaks)Eddie Hung2019-09-262-7/+3
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| * | | | | | Update docEddie Hung2019-09-261-1/+2
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| * | | | | | Zero out portsEddie Hung2019-09-261-2/+2
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| * | | | | | xilinx_dsp_cascade to also cascade AREG and BREGEddie Hung2019-09-262-454/+172
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| * | | | | | Try recursive pmgen for P cascadeEddie Hung2019-09-261-88/+118
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| * | | | | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run onceEddie Hung2019-09-261-9/+4
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| * | | | | | TypoEddie Hung2019-09-261-1/+1
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| * | | | | | CREG to check for \keepEddie Hung2019-09-261-0/+3
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