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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 10:59:56 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-30 10:59:56 -0700 |
| commit | a274b7cc86d4f64541d3d2903b4eeed4616ab1d8 (patch) | |
| tree | 0c72b8b167268b23d8b9327597d9cb553cb14942 | |
| parent | 5c5881695dd6570b933eccfd323f8b0e60b62718 (diff) | |
| download | yosys-a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.tar.gz yosys-a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.tar.bz2 yosys-a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.zip | |
Update doc for equiv_opt
| -rw-r--r-- | passes/equiv/equiv_opt.cc | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/passes/equiv/equiv_opt.cc b/passes/equiv/equiv_opt.cc index 9fe3bbd57..4ab5b1a3e 100644 --- a/passes/equiv/equiv_opt.cc +++ b/passes/equiv/equiv_opt.cc @@ -32,7 +32,8 @@ struct EquivOptPass:public ScriptPass log("\n"); log(" equiv_opt [options] [command]\n"); log("\n"); - log("This command checks circuit equivalence before and after an optimization pass.\n"); + log("This command uses temporal induction to check circuit equivalence before and\n"); + log("after an optimization pass.\n"); log("\n"); log(" -run <from_label>:<to_label>\n"); log(" only run the commands between the labels (see below). an empty\n"); @@ -156,7 +157,7 @@ struct EquivOptPass:public ScriptPass if (check_label("prove")) { if (multiclock || help_mode) run("clk2fflogic", "(only with -multiclock)"); - else + if (!multiclock || help_mode) run("async2sync", "(only without -multiclock)"); run("equiv_make gold gate equiv"); if (help_mode) |